參數(shù)資料
型號(hào): DS21Q55DK
英文描述: Quad T1/E1/J1 Transceiver Design Kit Daughter Card
中文描述: 四路T1/E1/J1收發(fā)器開(kāi)發(fā)板子卡
文件頁(yè)數(shù): 66/99頁(yè)
文件大小: 325K
代理商: DS21Q55DK
DS21Q50
Page 66 of 99
19. LINE INTERFACE UNIT
The line interface unit in the DS21Q50 contains three sections; (1) the receiver which handles clock and data
recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. The Line
Interface Control Register (LICR) which is described below controls each of these three sections.
Register Name:
LICR
Register Description:
LINE INTERFACE CONTROL REGISTER
Register Address:
17 Hex
Bit #
7
6
5
4
SYM
L2
L1
L0
EGL
JAS
SYMBOL
BIT NAME AND DESCRIPTION
L2
7
Line Build Out Select Bit 2.
Sets the transmitter build out. See Table
19-1.
L1
6
Line Build Out Select Bit 1.
Sets the transmitter build out. See Table
19-1.
L0
5
Line Build Out Select Bit 0.
Sets the transmitter build out. See Table
19-1.
EGL
4
Receive Equalizer Gain Limit.
0 = –12 dB
1 = –43 dB
JAS
3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
0
Transmit Power Down.
0 = powers down the transmitter and 3-states the TTIP and TRING
pins
1 = normal transmitter operation
3
2
1
0
JABDS
DJA
TPD
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