參數(shù)資料
型號(hào): DS21Q55DK
英文描述: Quad T1/E1/J1 Transceiver Design Kit Daughter Card
中文描述: 四路T1/E1/J1收發(fā)器開發(fā)板子卡
文件頁數(shù): 64/99頁
文件大小: 325K
代理商: DS21Q55DK
DS21Q50
Page 64 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
NRZE
SYMBOL
OUTBC
OUTB CONTROL REGISTER
1B Hex
7
6
-
5
-
4
3
2
1
0
OB4
OB3
OB2
OB1
OB0
BIT
7
NAME AND DESCRIPTION
NRZ Enable.
When this bit is set, the receiver can accept TTL type
NRZ data at the RTIP input. RRING becomes a clock input.
0 = RTIP and RRING are in normal mode
1 = RTIP becomes an NRZ TTL type input and RRING is its
associated clock input. Data at RTIP is clocked in on the falling edge of
the clock present on RRING.
Unused.
Should Be set = 0 for proper operation
Unused.
Should Be set = 0 for proper operation
OUTB control bit 4.
Inverts OUTB output
OUTB control bit 3.
See Table 18-1 for details
OUTB control bit 2.
See Table 18-1 for details
OUTB control bit 1.
See Table 18-1 for details
OUTB control bit 0.
See Table 18-1 for details
NRZE
-
-
6
5
4
3
2
1
0
OB4
OB3
OB2
OB1
OB0
Table 18-1 OUTA AND OUTB FUNCTION SELECT
OA3
OB3
OB2
OB1
OB0
0
0
0
0
External Hardware Control Bit
. In this mode OUTA and
OUTB can be used as simple control pins for external circuitry.
Use OA4 and OB4 to toggle OUTA and OUTB.
0
0
0
1
RCLK
. Receive Recovered Clock
0
0
1
0
Receive Loss Of Sync Indicator
. Real-time hardware version
of SR1.0. See Table 8-1.
0
0
1
1
Receive Loss Of Carrier Indicator
. Real-time hardware
version of SR1.1. See Table 8-1.
0
1
0
0
Receive Remote Alarm Indicator
. Real-time hardware
version of SR1.2. See Table 8-1.
0
1
0
1
Receive Unframed All Ones Indicator
. Real-time hardware
version of SR1.3. See Table 8-1.
0
1
1
0
Receive Slip Occurrence Indicator
. One clock wide pulse for
every slip of the receive elastic store. Hardware version of
SR1.4.
0
1
1
1
Receive CRC Error Indicator
. One clock wide pulse for
every multiframe that contains a CRC error. Output forced to 0
during loss of sync.
OA2
OA1
OA0
FUNCTION
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