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參數(shù)資料
| 型號： | DS21Q55DK |
| 英文描述： | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| 中文描述： | 四路T1/E1/J1收發(fā)器開發(fā)板子卡 |
| 文件頁數(shù)： | 76/99頁 |
| 文件大小： | 325K |
| 代理商： | DS21Q55DK |
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DS21Q50
Page 76 of 99
21. INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to
simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to
be multiplexed into higher speed data buses eliminating external hardware, saving board space and cost. The
DS21Q50 uses a channel interleave method. See Figure 22-4 and Figure 22-7 for details of the channel
interleave.
The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096 MHz bus speed allows two PCM
data streams to share a common bus. The 8.192 MHz bus speed allows four PCM data streams to share a
common bus. The 16.384 MHz bus speed allows 8 PCM data streams to share a common bus. See Figure 21-1
for an example of 4 transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each
transceiver must be enabled. Via the IBO register the user can configure each transceiver for a specific bus
speed and position. For all IBO bus configurations each transceiver is assigned an exclusive position in the high
speed PCM bus. When the device is configured for IBO operation, the TSYNCx pin should be configured as an
output or as an input connected to ground. The user cannot supply a TSYNCx signal in this mode.
Register Name:
IBO
Register Description:
INTERLEAVE BUS OPERATION REGISTER
Register Address:
1B Hex
Bit #
7
6
5
4
SYM
-
IBOTCS
SCS1
SCS0
SYMBOL
BIT
NAME AND DESCRIPTION
-
7
Not Assigned.
Should be set to 0.
IBOTCS
6
IBO Transmit Clock Source.
0 = TCLK pin will be source of transmit clock
1 = Transmit clock will internally derived from the clock at the SYSCLK pin
SCS1
5
System Clock Select bit 1
See
Table
21-2
SCS0
4
System Clock Select bit 0
See
Table
21-2
IBOEN
3
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
DA2
2
Device Assignment bit 3
See Table 21-1
DA1
1
Device Assignment bit 2
See Table 21-1
DA0
0
Device Assignment bit 1
See Table 21-1
3
2
1
0
IBOEN
DA2
DA1
DA0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad T1/E1/J1 Transceiver |
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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