參數(shù)資料
型號： DS26303LN-75+A3
廠商： Maxim Integrated Products
文件頁數(shù)： 17/101頁
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 144-LQFP 裸露焊盤
包裝： 托盤
其它名稱： 90-26303+7N3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
22 of 101
Figure 4-4. Serial Port Operation for Read Access with CLKE = 1
1
2
3
4
56
78
9
10
11
12
13
14
15
16
0
A1
A2
A3
A4
A5
D1
D2
D3
D4
D5
D6
SCLK
SDI
SDO
CSB
(lsb)
(msb)
D0
(lsb)
D7
(msb)
A6
X
4.1.3
Parallel Port Operation
When using the parallel interface on the DS26303 the user has the option for either multiplexed bus operation or
non-multiplexed bus operation. The ALE pin is pulled high in non-multiplexed bus operation. The DS26303 can
operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if the MODESEL pin is pulled high. The following table lists all
the pins and their functions in the parallel port mode. See the timing diagrams in Section 10 for more details.
Table 4-3. Parallel Port Mode Selection and Pin Functions
MODESEL, MOTEL,
MUX
PARALLEL HOST
INTERFACE
ADDRESS, DATA, AND CONTROL
100
Non-multiplexed Motorola
CSB, ACKB, DSB, RWB, ASB, A[4:0], D[7:0],
INTB
110
Non-multiplexed Intel
CSB, RDY, WRB, RDB, ALE, A[4:0], D[7:0],
INTB
101
Multiplexed Motorola
CSB, ACKB, DSB, RWB, ASB, AD[7:0],
INTB
111
Multiplexed Intel
CSB, RDY, WRB, RDB, ALE, AD[7:0],
INTB
4.1.4
Interrupt Handling
INTB must be pulled high externally with a 10k
Ω resistor for wired-OR operation. If a wired-OR operation is not
required, the
INTB pin can be configured to be high when not active by setting register GISC.INTM.
There are three events that can potentially trigger an interrupt: a loss of signal (LOS), driver fault monitor (DFM), or
an alarm indication signal (AIS). The interrupt functions as follows:
When a status bit (AIS:AISn, DFMS:DFMSn, or LOSS:LOSn) changes on an interruptible event, the
corresponding interrupt status bit (AISIS:AISIn, DFMIS:DFMISn, or LOSIS:LOSISn) is set. The
INTB pin will go
low if the event is enabled through the corresponding interrupt-enable bit (AISIE:AISIEn, DFMIE:DFMIEn, or
When an interrupt occurs, the host processor must read the three interrupt status registers (AISIS, DFMIS, and
LOSIS) to determine the source of the interrupt. If the interrupt status registers are set for clear-on-read
(GISC.CWE reset), the read also clears the interrupt status register, which clears the output
INTB pin. If the
interrupt status registers are set for clear-on-write (GISC.CWE set), a 1 must be written to the interrupt status
bit (AISIS:AISIn, DFMIS:DFMISn, or LOSIS:LOSISn) in order to clear it, which clears the output
INTB pin.
Subsequently, the host processor can read the corresponding status register (AIS, DFMS, or LOSS) to check
the real-time status of the event.
Note:
The BERT can also generate an interrupt. The BERT interrupt handling is described in Section 6.9.2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303LN-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26-32.768-STD-020 制造商:Micro Crystal Switzerland 功能描述:
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