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參數(shù)資料
| 型號： | DS26303LN-75+A3 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/101頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 90-26303+7N3 |
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
101 of 101
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m In tegra t ed P r oduc ts , 1 2 0 S a n Ga brie l D r iv e , Sun ny vale , CA 94 086 40 8 - 7 3 7 - 76 00
2007 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
REVISION
DESCRIPTION
(Page 30) LOSS: added missing “S” to bit names (from LOS[8:1] to LOSS[8:1]); DFMS: changed
bit description for bits 7 to 0.
(Page 31) LOSIS: changed bit description for bits 7 to 0; DFMIS: changed bit description for bits
7 to 0.
(Page 33) DLBC: changed register description from Digital Loopback Control to Digital Loopback
Configuration and added note to bits 7 to 0 description.
(Page 34) GC: updated descriptions for bits 7 to 0.
(Page 35) TST: changed register description from Template Select Transmitter to Template
Select Transceiver.
(Page 36) OEB: updated bits 7 to 0 description.
(Page 37) AISI: added “S” and “Status” to register name and description; updated bit names and
description; ADDP: changed register description from Address Pointer to Address Pointer for
Bank Selection.
(Page 38) TPDE: corrected bits 7 to 0 name from TPDE[7:0] to TPDE[8:1].
(Page 39) EZDE: corrected bits 7 to 0 name from EXZDE[8:1] to EZDE[8:1].
(Page 40) IJAPS: updated bits 7 to 0 description; IJAFLT: corrected bits 7 to 0 name to show
read-only (added underline) and added sentence at end of description.
(Page 43) GMR: changed bits 2 and 1 from Reserved to JABWS1 and JABWS0.
(Page 44) LVDS: added information on when the bit is cleared.
(Page 54) Section 6.1: Power-Up and Reset. Deleted “A reset can also be performed in software
by writing to SWR register.”
(Page 55) Section 6.3: Transmitter. In second paragraph, first sentence, “The data is encoded
with HDB3 or B8ZS or NRZ encoding …” changed NRZ to AMI.
(Page 59) Section 6.3.3: Dual-Rail Mode, Section 6.3.4: Single-Rail Mode, and Section 6.4:
Receiver. Updated paragraphs.
(Page 65) Section 6.8.3: Remote Loopback. Added information about when the TCLKn pin is
ignored.
(Page 67) Added new Section 6.8.4: Dual Loopback and Figure 6-11.
(Page 69) Added new Section 6.9.2: BERT Interrupt Handling.
(Page 80) Table 10-2: added Analog Loss-of-Signal Threshold Hysteresis parameter; updated
Note 1.
(Page 97) Added new Section 11: Pin Configuration.
053107
(Page 78) Table 8-3: added “Note 1: Specifications to -40
°C are guaranteed by design (GBD).”
(Pages 81, 84, 87, 90) Table 10-3, 10-4, 10-5, 10-6: added “Note 1: Timing parameters in this
table are guaranteed by design (GBD).”
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26-32.768-STD-020 | 制造商:Micro Crystal Switzerland 功能描述: |
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