參數(shù)資料
型號(hào)： DS26303LN-75+A3
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 63/101頁(yè)
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 線(xiàn)路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 144-LQFP 裸露焊盤(pán)
包裝： 托盤(pán)
其它名稱(chēng)： 90-26303+7N3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
64 of 101
6.6
Jitter Attenuator
The DS26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the JADS
bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register. The 128-
bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-
sensitive applications. The characteristics of the attenuation are shown in Figure 6-7. The jitter attenuator can be
placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE bits in
register GC. These selections can be changed on an individual LIU basis by settings in the IJAPS and IJAE.
66666
For the jitter attenuator to properly operate, a 2.048MHz or multiple thereof, or 1.544MHz clock or multiple thereof
must be applied at MCLK. ITU-T specification G.703 requires an accuracy of ±50ppm for both T1 and E1
applications. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board circuitry adjusts
either the recovered clock from the clock/data recovery block or the clock applied at the TCLKn pin to create a
smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLKn pin if the jitter attenuator is placed on the transmit side. If the incoming jitter
exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the DS26303 divides the
internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the
buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip
(IJAFLTn) bits in the IJAFLT register described.
Figure 6-7. Jitter Attenuation
FREQUENCY (Hz)
0dB
-20dB
-40dB
-60dB
1
10
100
1K
10K
JITTER
ATTENUAT
ION
(dB)
100K
TR 62411 (Dec. 90)
Prohibited Area
C
urv
e
B
Cu
rv
e
A
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
T1
E1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303LN-XXX 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-XXX+ 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX+ 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26-32.768-STD-020 制造商:Micro Crystal Switzerland 功能描述:
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