- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1915 > DS26303LN-75+A3 (Maxim Integrated Products)IC LIU E1/T1/J1 3.3V 144-ELQFP PDF資料下載
參數(shù)資料
| 型號： | DS26303LN-75+A3 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 73/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 90-26303+7N3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當(dāng)前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
73 of 101
7.1
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of TCLK.
The state diagram is shown in Figure 7-2.
7.1.1
Test-Logic-Reset
Upon power-up, the TAP controller will be in the Test-Logic-Reset state. The instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally. This state is automatically entered during
power-up. This state is entered from any state if the JTMS is held high for at least 5 clocks.
7.1.2
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test
registers will remain idle. The controller remains in this state when JTMS is held low. When the JTMS is high and
rising edge of TCLK is applied the controller moves to the Select-DR-Scan state.
7.1.3
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of TCLK moves the controller into the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on TCLK moves the controller
to the Select-IR-Scan state.
7.1.4
Capture-DR
Data can be parallel-loaded into the test-data registers if the current instruction is EXTEST or SAMPLE/PRELOAD.
If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of TCLK, the controller will go to the Shift-DR state if
JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
7.1.5
Shift-DR
The test-data register selected by the current instruction will be connected between JTDI and JTDO and will shift
data one stage towards its serial output on each rising edge of TCLK. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state. When the TAP controller is in this state
and a rising edge of TCLK is applied, the controller enters the Exit1-DR state if JTMS is high or remains in Shift-DR
state if JTMS is low.
7.1.6
Exit1-DR
While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on TCLK with JTMS LOW will put the controller in the Pause-DR
state.
7.1.7
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on TCLK with
JTMS HIGH will put the controller in the Exit2-DR state.
7.1.8
Exit2-DR
A rising edge on TCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on TCLK with JTMS LOW will enter the Shift-DR state.
7.1.9
Update-DR
A falling edge on TCLK while in the Update-DR state will latch the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS26324GNA2+ | IC INTERFACE LINE 16CH 256-CSBGA |
| DS26334GN+ | IC INTERFACE LINE 16CH 256-CSBGA |
| DS26401N+ | IC OCTAL FRAMER T1/E1/J1 256-BGA |
| DS26504LNB2+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS26514G+ | IC TXRX T1/E1/J1 4PORT 256-CSBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26-32.768-STD-020 | 制造商:Micro Crystal Switzerland 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。