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參數(shù)資料
| 型號(hào)： | DS3106LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 28/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS3106
34
7.8.2.6 Custom Output Frequencies
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MHz, any multiple of 8kHz up to 311.04MHz, and any multiple of 10kHz up to 388.79MHz. (An APLL must be
used to achieve frequencies above 77.76MHz.) Any of the programmable output clocks can be configured to output
the custom frequency or submultiples thereof. Contact Microsemi timing products technical support for help with
custom frequencies.
7.9
Microprocessor Interface
The DS3106 presents an SPI interface on the
CS, SCLK, SDI, and SDO pins. SPI is a widely used master/slave
bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. The
DS3106 is always a slave device. Masters are typically microprocessors, ASICs, or FPGAs. Data transfers are
always initiated by the master device, which also generates the SCLK signal. The DS3106 receives serial data on
the SDI pin and transmits serial data on the SDO pin. SDO is high impedance except when the DS3106 is
transmitting data to the bus master.
Bit Order. When both bit 3 and bit 4 are low at device address 3FFFh, the register address and all data bytes are
transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the
register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and
Motorola SPI convention is MSB first.
Clock Polarity and Phase. SCLK is normally low and pulses high during bus transactions. The CPHA pin sets the
phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on the leading edge of the SCLK pulse
and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the trailing edge of the
SCLK pulse and updated on SDO on the following leading edge. SCLK does not have to toggle between accesses,
i.e., when
CS is high. See Figure 7-4.
Device Selection. Each SPI device has its own chip-select line. To select the DS3106, pull its
CS pin low.
Control Word. After
CS is pulled low, the bus master transmits the control word during the first 16 SCLK cycles. In
MSB-first mode the control word has the form:
R/
W A13 A12 A11 A10 A9 A8 A7
A6 A5 A4 A3 A2 A1 A0 BURST
where A[13:0] is the register address, R/
W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/
W = 1 is a read control word, while a control word with R/W = 0 is a
write control word.
Single-Byte Writes. See Figure 7-5. After
CS goes low, the bus master transmits a write control word with
BURST = 0, followed by the data byte to be written. The bus master then terminates the transaction by pulling
CS
high.
Single-Byte Reads. See Figure 7-5. After
CS goes low, the bus master transmits a read control word with
BURST = 0. The DS3106 then responds with the requested data byte. The bus master then terminates the
transaction by pulling
CS high.
Burst Writes. See Figure 7-5. After
CS goes low, the bus master transmits a write control word with BURST = 1
followed by the first data byte to be written. The DS3106 receives the first data byte on SDI, writes it to the
specified register, increments its internal address register, and prepares to receive the next data byte. If the master
continues to transmit, the DS3106 continues to write the data received and increment its address counter. After the
address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.
Burst Reads. See Figure 7-5. After
CS goes low, the bus master transmits a read control word with BURST = 1.
The DS3106 then responds with the requested data byte on SDO, increments its address counter, and prefetches
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS3106LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3107FP000 | 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V |
| DS3107FRAB0 | 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC |
| DS3107MP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V |
| DS3107MP00K | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC |
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