參數(shù)資料
型號(hào): DS3106LN+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 70/92頁(yè)
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 1429 (CN2011-ZH PDF)
DS3106
72
Register Name:
FSCR1
Register Description:
Frame-Sync Configuration Register 1
Register Address:
7Ah
Bit #
7
6
5
4
3
2
1
0
Name
8KINV
8KPUL
2KINV
2KPUL
Default
0
Bit 3: 8kHz Invert (8KINV). When this bit is set to 1, the 8kHz signal on clock output FSYNC is inverted. See
Section 7.8.2.5.
0 = FSYNC not inverted
1 = FSYNC inverted
Bit 2: 8kHz Pulse (8KPUL). When this bit is set to 1, the 8kHz signal on clock output FSYNC is pulsed rather than
50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the
clock period of OC3. See Section 7.8.2.5.
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
Bit 1: 2kHz Invert (2KINV). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is inverted. See
Section 7.8.2.5.
0 = MFSYNC not inverted
1 = MFSYNC inverted
Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather
than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to
the clock period of OC3. See Section 7.8.2.5.
0 = MFSYNC not pulsed; 50% duty cycle
1 = MFSYNC pulsed, with pulse width equal to OC3 period
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