參數(shù)資料
型號(hào): DS3106LN+
廠商: Maxim Integrated Products
文件頁數(shù): 54/92頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS3106
58
Register Name:
DLIMIT3
Register Description:
DPLL Frequency Limit Register 3
Register Address:
4Dh
Bit #
7
6
5
4
3
2
1
0
Name
FLLOL
SOFTLIM[6:0]
Default
1
0
1
0
Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL internally declares loss-of-
lock when the hard frequency limit in the DLIMIT1 and DLIMIT2 registers is reached. See Section 7.7.5.
0 = DPLL declares loss-of-lock normally.
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached.
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM[6:0]). This field is an unsigned integer that specifies the soft
frequency limit for the T0 DPLL. The soft limit is only used for monitoring; exceeding this limit does not cause loss-
of-lock. The limit in ppm is
±SOFTLIM[6:0] × 0.628. The default value is ±8.79ppm. When the T0 DPLL frequency
reaches the soft limit, the T0SOFT status bit is set in the OPSTATE register. See Section 7.7.5.
Register Name:
IER4
Register Description:
Interrupt Enable Register 4
Register Address:
4Eh
Bit #
7
6
5
4
3
2
1
0
Name
HORDY
Default
0
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). This bit is an interrupt enable for the HORDY
bit in the MSR4 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
OCR5
Register Description:
Output Configuration Register 1
Register Address:
4Fh
Bit #
7
6
5
4
3
2
1
0
Name
AOF6
AOF3
Default
0
Bit 5: Alternate Output Frequency Mode Select 6 (AOF6). This bit controls the decoding of the OCR3.OFREQ6
field for the OC6 pin.
0 = Standard decodes
1 = Alternate decodes
Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). This bit controls the decoding of the OCR2.OFREQ3
field for the OC3 pin.
0 = Standard decodes
1 = Alternate decodes
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