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參數(shù)資料
| 型號(hào)： | DS3141+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3/E3 SNGL 144CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 80mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 144-TECSBGA（13x13） |
| 包裝： | 托盤 |
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
19 of 88
Figure 7-2. Transmit Clock Block Diagram
7.2.2 Loss-of-Clock Detection
The LOTC and LORC (loss-of-receive clock) status bits in the MSR register are set when the transmit (TICLK) and
receive (RCLK) clocks are stopped, respectively. The clocks are monitored with the system clock (SCLK), which
must be running for the loss-of-clock circuits to function properly. The LOTC and LORC status bits are set when
TICLK or RCLK have been stopped high or low for between 9 and 21 clock periods (depending on SCLK
frequency). The LOTC and LORC status bits are cleared after the device detects a few edges of the monitored
clock.
7.3 Receiver Logic
In the normal operating mode, the signals on RPOS and RNEG are decoded as an HDB3 signal in E3 mode or as
a B3ZS signal in DS3 mode and output on the RDAT pin. The input signal is monitored for loss-of-signal, bipolar
violations, excessive zeroes, AIS, and unframed all ones, and after decoding, is sent to the BERT and
synchronizer. When the synchronizer finds the framing pattern in the overhead bits, it clears the out-of-frame
indication (ROOF) and aligns the start-of-frame (RSOF) and data-enable (RDEN) signals to the signal on RDAT. If
the framing pattern is lost, then ROOF is set and the framing pattern is searched for again. While the framing
pattern is being searched for, the RSOF and RDEN signals maintain the alignment with the last known position of
the framing pattern. If a framing pattern is found in a new position, the RSOF and RDEN signals align with the new
pattern position and the COFAL status bit is set in the T3E3SRL register. After reset, the RSOF and RDEN signals
are generated, but have no relationship with any framing pattern until one is found. The signal on the ROOF pin
can be monitored using the OOF bit in the T3E3SR register. When the diagnostic loopback mode is enabled using
the DLB bit in the MC2 register, RCLK, RPOS, and RNEG are replaced with TICLK, TPOS, and TNEG. This allows
the framer and synchronizer logic to be checked in order to isolate a problem in the system. The BERT can monitor
either the payload or the entire signal for expected test patterns.
Figure 7-3. Receiver Block Diagram
LOTC
RCLK
TCLK
TICLK
INTERNAL TCLK
LOTCMC
LLB
PLB
0
1
LORC
Rx BERT
DS3
E3 G.751
SYNCHRONIZER
HDB
B3ZS
AMI
DECODER
RPOS
RNEG
RCLK
ROCLK
FROM Tx DLB
DLB
RDAT
RLOS
ROOF
RSOF
RDEN
FROM Tx BERT
TDAT
TO PLB MUX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3141+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS314-1010NR WAF | 制造商:ON Semiconductor 功能描述: |
| DS31412 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31412N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31415 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
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