- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1915 > DS3141+ (Maxim Integrated Products)IC FRAMER DS3/E3 SNGL 144CSBGA PDF資料下載
參數(shù)資料
| 型號： | DS3141+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3/E3 SNGL 144CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 80mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 144-TECSBGA（13x13） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
49 of 88
Register Name:
BSRL
Register Description:
BERT Status Register Latched
Register Address:
39h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RA1L
RA0L
BEDL
BBCOL
BECOL
SYNCL
Default
—
Note: See Figure 7-6 for details on the interrupt logic for the status bits in the BSRL register.
Bit 0: Synchronization Status Latched (SYNCL). This latched status bit is set to 1 when the SYNC status bit in
the BSR register changes state (low to high or high to low). To determine if this bit was set because of finding
synchronization or losing synchronization, read the SYNC real-time status bit in the BSR register. SYNCL is
cleared when the host processor writes a 1 to it and is not set again until SYNC changes state again. When
SYNCL is set, it can cause a hardware interrupt to occur if the SYNCIE bit in the BSRIE register and the BERTIE
bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the
interrupt-enable bits are cleared.
Bit 1: BERT Error-Counter Overflow Latched (BECOL). This latched status bit is set to 1 when the BECO status
bit in the BSR register goes high. BECOL is cleared when the host processor writes a one to it and is not set again
until BECO goes high again. When BECOL is set, it can cause a hardware interrupt to occur if the BECOIE bit in
the BSRIE register and the BERTIE bit in the MSRIE register are both set to a 1. The interrupt is cleared when this
bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 2: BERT Bit-Counter Overflow Latched (BBCOL). This latched status bit is set to 1 when the BBCO status bit
in the BSR register goes high. BBCOL is cleared when the host processor writes a 1 to it and is not set again until
BBCO goes high again. When BBCOL is set, it can cause a hardware interrupt to occur if the BBCOIE bit in the
BSRIE register and the BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is
cleared or one or both of the interrupt-enable bits are cleared.
Bit 3: Bit Error-Detected Latched (BEDL). This latched status bit is set to 1 when a bit error is detected. The
receive BERT must be in synchronization to detect bit errors. BEDL is cleared when the host processor writes a 1
to it. When BEDL is set it can cause a hardware interrupt to occur if the BEDIE bit in the BSRIE register and the
BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both
of the interrupt-enable bits are cleared.
Bit 4: Receive All-Zeros Latched (RA0L). This latched status bit is set to 1 when the RA0 bit in the BSR register
is set. RA0L is cleared when the host processor writes a 1 to it. RA0L cannot cause an interrupt.
Bit 5: Receive All-Ones Latched (RA1L). This latched status bit is set to 1 when the RA1 bit in the BSR register is
set. RA1L is cleared when the host processor writes a 1 to it. RA1L cannot cause an interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
| DS3154N+ | IC LIU DS3/E3/STS-1 QD 144CSBGA |
| DS3164+ | IC ATM/PACKET PHY QUAD 400-BGA |
| DS3170+ | IC TXRX DS3/E3 100-CSBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3141+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS314-1010NR WAF | 制造商:ON Semiconductor 功能描述: |
| DS31412 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31412N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31415 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。