參數(shù)資料
型號： DS3141+
廠商： Maxim Integrated Products
文件頁數(shù)： 18/88頁
文件大?。?/td> 0K
描述： IC FRAMER DS3/E3 SNGL 144CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 80mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 托盤
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
25 of 88
Register Name:
MC3
Register Description:
Master Configuration Register 3
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
TDENMS
TSOFC
TOHENI
TOHI
TSOFI
TICLKI
TDATI
TDENI
Default
0
Bit 0: TDEN Invert Enable (TDENI)
0 = do not invert the TDEN/TGCLK signal (normal mode)
1 = invert the TDEN/TGCLK signal (inverted mode)
Bit 1: TDAT Invert Enable (TDATI)
0 = do not invert the TDAT signal (normal mode)
1 = invert the TDAT signal (inverted mode)
Bit 2: TICLK Invert Enable (TICLKI)
0 = do not invert the TICLK signal (normal mode)
1 = invert the TICLK signal (inverted mode)
Bit 3: TSOF Invert Enable (TSOFI)
0 = do not invert the TSOF signal (normal mode)
1 = invert the TSOF signal (inverted mode)
Bit 4: TOH Invert Enable (TOHI)
0 = do not invert the TOH signal (normal mode)
1 = invert the TOH signal (inverted mode)
Bit 5: TOHEN Invert Enable (TOHENI)
0 = do not invert the TOHEN signal (normal mode)
1 = invert the TOHEN signal (inverted mode)
Bit 6: Transmit Start-of-Frame I/O Control (TSOFC). When this bit is logic 1, the TSOF pin is an output and
pulses for the last TICLK cycle of each frame. When this bit is 0, the TSOF pin is an input, and the device uses it to
determine the frame boundaries. See Figure 5-1 for functional timing information.
0 = TSOF is an input (reset default as input)
1 = TSOF is an output
Bit 7: Transmit Data-Enable Mode Select (TDENMS). When this bit is logic 0, the TDEN/TGCLK output has the
TDEN (data enable) function. TDEN asserts during payload bit times and de-asserts during overhead bit times.
When this bit is logic 1, TDEN/TGCLK has the TGCLK (gapped clock) function. TGCLK pulses during payload bit
times and is suppressed during overhead bit times. The TCCLK control bit in the MC2 register has precedence
over this control bit. See Figure 5-1 for functional timing information.
0 = TDEN (data enable) mode
1 = TGCLK (gapped clock) mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3141+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS314-1010NR WAF 制造商:ON Semiconductor 功能描述:
DS31412 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS31412N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS31415 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock
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