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| 型號(hào)： | DS3171 |
| 英文描述： | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| 中文描述： | 單/雙/三/四路、DS3/E3單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 210/232頁(yè) |
| 文件大?。?/td> | 2133K |
| 代理商： | DS3171 |
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DS3171/DS3172/DS3173/DS3174
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Table 13-1. JTAG Instruction Codes
INSTRUCTIONS
EXTEST
IDCODE
SAMPLE/PRELOAD
CLAMP
HIGHZ
—
—
BYPASS
SELECTED REGISTER
Boundary Scan
Device Identification
Boundary Scan
Bypass
Bypass
Bypass
Bypass
Bypass
INSTRUCTION CODES
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD.
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports
two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with
the normal operation of the device and the boundary scan register can be pre-loaded for the EXTEST instruction.
The positive edge of JTCLK in the Capture
-
DR state samples all digital input pins into the boundary scan register.
The boundary scan register is connected between JTDI and JTDO. The data on JTDI pin is clocked into the
boundary scan register and the data captured in the Capture-DR state is shifted out the TDO pin in the Shift
-
DR
state.
EXTEST.
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction allows testing of all
interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following
actions occur. Once enabled by the Update
-
IR state, the parallel outputs of all digital output pins are driven
according to the values in the boundary scan registers on the positive edge of JTCLK. The boundary scan register
is connected between JTDI and JTDO. The positive edge of JTCLK in the Capture
-
DR state samples all digital
input pins into the boundary scan register. The negative edge of JTCLK in the Update-DR state causes all of the
digital output pins to be driven according to the values in the boundary scan registers that have been shifted in
during the Shift-DR state. The outputs are returned to their normal mode or HIZ mode at the positive edge of
JTCLK during the Update-IR state when an instruction other than EXTEST or CLAMP is activated.
BYPASS.
This is a mandatory instruction for the IEEE 1149.1 specification. When the BYPASS instruction is
latched into the parallel instruction register, JTDI connects to JTDO through the 1
-
bit bypass test register. This
allows data to pass from JTDI to JTDO not affecting the device’s normal operation. This mode can be used to
bypass one or more chips in a system with multiple chips that have their JTAG scan chain connected in series. The
chips not in bypass can then be tested with the normal JTAG modes.
IDCODE.
This is a mandatory instruction for the IEEE 1149.1 specification. When the IDCODE instruction is
latched into the parallel instruction register, the identification test register is selected. The device identification code
is loaded into the identification register on the rising edge of JTCLK following entry into the Capture
-
DR state. Shift
-
DR can be used to shift the identification code out serially through JTDO. During Test
-
Logic
-
Reset, the
identification code is forced into the instruction register’s parallel output.
HIGHZ.
All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO. The outputs are put into the HIZ mode when the HIZ instruction is loaded in the Update-IR state and on
the positive edge of JTCLK. The outputs are returned to their normal mode or driven from the boundary scan
register at the positive edge of JTCLK during the Update-IR state when an instruction other than HIZ is activated.
CLAMP.
All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction. If the previous
instruction was not EXTEST, the outputs will be driven according to the values in the boundary scan register at the
positive edge of JTCLK in the Update-IR state. The typical use of this instruction is in a system that has the JTAG
scan chain of multiple chips connected in series, and all of the chips have their outputs initialized using the
EXTEST mode. Then some of the chips are left initialized using the CLAMP mode and others have their IO
controlled using the EXTEST mode. This reduces the size of the scan chain during the partial testing of the system.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3173 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3173N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3171N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3171N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3172 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3172+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3172N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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