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| 型號(hào)： | DS3172N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 204/234頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX DS3/E3 DUAL 400-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 4 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | DS3，E3 |
| 電路數(shù)： | 2 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 328mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 管件 |
| 包括： | DS3 調(diào)幀器，E3 調(diào)幀器，HDLC 控制器，芯片內(nèi) BERT |
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DS3171/DS3172/DS3173/DS3174
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10.5.1.2 Line Loopback (LLB)
Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and LLB are enabled at the same time when
LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010.
The clock from the receive LIU or the RLCLKn pin will be output to the transmit LIU or TCLKOn pin. The POS and
NEG data from the receive LIU or the RPOSn and RNEGn pin will be sampled with the receive clock to time it to
the LIU or pin interface.
When LLB is enabled, unframed all ones AIS can optionally be automatically enabled on the receive data path.
This AIS signal will be output on the RSERn pin in SCT modes. When DLB and LLB are enabled, the AIS signal
will not be transmitted.
Refer to Figure 10-10.
10.5.1.3 Payload Loopback (PLB)
Payload loopback is enabled by setting PORT.CR4.LBM[2:0] = 011.
The payload loopback copies the payload data from the receive framer to the transmit framer which then re-frames
the payload before transmission. Payload loopback is operational in all framing modes.
When PLB is enabled, unframed all ones AIS transmission can optionally be automatically enabled on the receive
data path. This AIS signal will be output on the RSER. In all PLB modes, the TSOFIn input pin is ignored.
The external transmit output pins TDENn and TSOFOn/TDENn can optionally be disabled by forcing a zero when
PLB is enabled.
Refer to Figure 10-10.
10.5.1.4 Diagnostic Loopback (DLB)
Diagnostic loopback is enabled by setting PORT.CR4.LBM[2:0] = 1XX. DLB and LLB are enabled at the same time
when LBM[2:0] = 110, only DLB is enabled when LBM[2:0] = 10X or 111.
The Diagnostic loopback sends the transmit data, before line encoding, back to the receive side.
Transmit AIS can still be enabled using PORT.CR1.LAIS[2:0] even when DLB is enabled.
Refer to Figure 10-10.
10.5.2 Loss Of Signal Propagation
The Loss Of Signal (LOS) is detected in the line decoder logic. In unipolar (UNI) line interface modes LOS is never
detected. The LOS signal from the line decoder is sent to the DS3/E3 framer and the top-level payload AIS logic
except when DLB is activated. When DLB is activated the LOS signal to the framer and AIS logic is never active.
The LOS status in the line decoder status register is valid in all frame and loop back modes, though it is always off
in the line interface is in the UNI mode.
10.5.3 AIS Logic
There is AIS logic in both the framers and at the top-level logic of the ports. The framer AIS is enabled by setting
the TAIS bit in the appropriate framer transmit control register (T3, E3-G.751, E3-G.832, or Clear Channel). The
top level AIS is enabled by setting the PORT.CR1.LAIS[2:0] bits (see Table 10-18). The AIS signal is an unframed
all ones pattern or a DS3 framed 101010… pattern depending on the FM[2:0] mode bits. The DS3 Framed Alarm
Indication Signal (AIS) is a DS3 signal with valid F-bits, M-bits, and P-bits (P1 and P2). The X-bits (X1 and X2) are
set to one, all C-bits (CXY) are set to zero, and the payload bits are set to a 1010 pattern starting with a one
immediately after each overhead bit. The DS3 framed AIS pattern is only available in DS3 modes. The unframed all
ones pattern is available in all framing modes including the DS3 modes. The transmit line interface can send both
unframed all ones AIS and DS3 framed AIS patterns from either the AIS generator in the framer or the AIS
generator at the top level.
The AIS signal generated in the framer can be initiated and terminated without introducing any errors in the signal.
When the unframed AIS signal is initiated or terminated, there will be no BPV or CV errors introduced, but there will
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| DS3172N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3173 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3173N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3174 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3174+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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