參數(shù)資料
型號： DS80C410-FNY+
廠商： Maxim Integrated Products
文件頁數(shù)： 30/102頁
文件大小： 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設(shè)備： 電源故障復位，WDT
輸入/輸出數(shù)： 64
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： ROM
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
33 of 102
PIN
NAME
FUNCTION
50
P6.6
P6.3
CE7
Program Memory Chip Enable 7
P6.4
A20 Program/Data Memory Address 20
P6.5
A21 Program/Data Memory Address 21
P6.6
RXD2 Serial Port 2 Receive
P6.7
TXD2 Serial Port 2 Transmit
49
P6.7
78
A0
Port 7, I/O. Port 7 can function as either an 8-bit, bidirectional I/O port or the nonmultiplexed A0–A7 signals
(when the MUX pin = 1). The reset condition of Port 7 is all bits at logic 1 through a weak pullup. The logic 1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written
to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,
followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
Alternate Function
P7.0
A0 Program/Data Memory Address 0
P7.1
A1 Program/Data Memory Address 1
P7.2
A2 Program/Data Memory Address 2
P7.3
A3 Program/Data Memory Address 3
P7.4
A4 Program/Data Memory Address 4
P7.5
A5 Program/Data Memory Address 5
P7.6
A6 Program/Data Memory Address 6
P7.7
A7 Program/Data Memory Address 7
77
A1
76
A2
75
A3
74
A4
73
A5
72
A6
71
A7
8
TXClk
Transmit Clock, Input. The transmit clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of TX_EN and TXD[3:0] signals from the MAC to the external
Ethernet PHY controller. The input clock frequency of TXClk should be 25MHz for 100Mbps operation and
2.5MHz for 10Mbps operation. For ENDEC operation, TXClk serves the same function, but the input clock
frequency should be 10MHz.
7
TX_EN
Transmit Enable, Output. The transmit enable is an active-high output and is synchronous with respect to the
TXClk signal. TX_EN is used to indicate valid nibbles of data for transmission on the MII pins TXD.3–TXD.0.
TX_EN is asserted with the first nibble of the preamble and remains asserted while all nibbles to be transmitted
are presented on the TXD.3–TXD.0 pins. TX_EN negates prior to the first TXClk following the final nibble of the
frame. TX_EN serves the same function for ENDEC operation.
3
TXD.3
Transmit Data, Output. The transmit data outputs provide 4-bit nibbles of data for transmission over the MII.
The transmit data is synchronous with respect to the TXClk signal. For each TXClk period when TX_EN is
asserted, TXD.3–TXD.0 provides the data for transmission to the Ethernet PHY controller. When TX_EN is
deasserted, the TXD data should be ignored. For ENDEC operation, only TXD.0 is used for transmission of
frames.
4
TXD.2
5
TXD.1
6
TXD.0
10
RXClk
Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of RX_DV, RX_ER, and RXD[3:0] signals from the external
Ethernet PHY controller to the MAC. The input clock frequency of RXClk should be 25MHz for 100Mbps
operation and 2.5MHz for 10Mbps operation. For ENDEC operation, RXClk serves the same function, but the
input clock frequency should be 10MHz.
11
RX_DV
Receive Data Valid, Input. The receive data valid is an active-high input from the external Ethernet PHY
controller and is synchronous with respect to the RXClk signal. RX_DV is used to indicate valid nibbles of data
for reception on the MII pins RXD.3–RXD.0. RX_DV is asserted continuously from the first nibble of the frame
through the final nibble. RX_DV negates prior to the first RXClk following the final nibble. RX_DV serves the
same function for ENDEC operation.
9
RX_ER
Receive Error, Input. The receive error is an active-high input from the external Ethernet PHY controller and is
synchronous with respect to the RXClk signal. RX_ER is used to indicate to the MAC that an error (e.g., a
coding error, or any error detectable by the PHY) was detected somewhere in the frame presently being
transmitted by the PHY. RX_ER has no effect on the MAC while RX_DV is deasserted. RX_ER should be low
for ENDEC operation.
17
RXD.3
Receive Data, Input. The receive data inputs provide 4-bit nibbles of data for reception over the MII. The
receive data is synchronous with respect to the RXClk signal. For each RXClk period when RX_DV is asserted,
RXD.3–RXD.0 have the data to be received by the MAC. When RX_DV is deasserted, the RXD data should be
ignored. For ENDEC operation, only RXD.0 is used for reception of frames.
16
RXD.2
15
RXD.1
14
RXD.0
1
CRS
Carrier Sense, Input. The carrier sense signal is an active-high input and should be asserted by the external
Ethernet PHY controller when either the transmit or receive medium is not idle. CRS should be deasserted by
the PHY when the transmit and receive mediums are idle. The PHY should ensure that the CRS signal remains
asserted throughout the duration of a collision condition. The transitions on the CRS signal need not be
synchronous to TXClk or RXClk. CRS serves the same function for ENDEC operation.
2
COL
Collision Detect, Input. The collision detect signal is an active-high input and should be asserted by the
external Ethernet PHY controller upon detection of a collision on the medium. The PHY should ensure that COL
remains asserted while the collision condition persists. The transitions on the COL signal need not be
synchronous to TXClk or RXClk. The COL signal is ignored by the MAC when operating in full-duplex mode.
COL serves the same function for ENDEC operation.
18
MDC
MII Management Clock, Output. The MII management clock is generated by the MAC for use by the external
Ethernet PHY controller as a timing referenced for transferring information on the MDIO pin. MDC is a periodic
signal that has no maximum high or low times. The minimum high and low times are 160ns each. The minimum
period for MDC is 400ns independent of the period of TXClk and RXClk.
相關(guān)PDF資料
PDF描述
DS8102+ IC MODULATOR/DECODER 16-TSSOP
DS8113-JNG+ IC INTERFACE SMART CARD 28-TSSOP
DS8313-RRX+ IC INTERFACE SMART CARD 28-SOIC
DS8500-JND+T&R IC MODEM HART SGL 3.6V 20-TQFN
DS87C520-ENL IC MCU EPROM/ROM 33MH IND 44TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS80C410-FNY+ 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
DS80C411 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN
DS80C411-FNY 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
DS80C411-FNY+ 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
DS80CH11 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:System Energy Manager
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*