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參數(shù)資料
| 型號(hào)： | DS80C410-FNY+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 54/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 75MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | ROM |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
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aborted. The BCU incorporates a 31 x 8 first-in-first-out receive packet register (receive FIFO) so that the CPU can
access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer
memory, the BCU writes a receive status word into the first word of the receive packet starting page, updates the
receive FIFO, and notifies the CPU by setting an interrupt flag. The CPU can access the receive FIFO by reading
the BCUD SFR. Bits 4–0 of the data read from BCUD contain the starting page address and bits 7, 6, 5 reflect the
number of pages occupied by the packet.
For a transmit operation, the tasks performed by the BCU are similar. The CPU first provides size/location
information of the transmit packet to the BCU. This is accomplished by three consecutive writes to the BCUD SFR.
The first write specifies the MSB of the 11-bit byte count for the transmit packet, the second gives the LSB of the
11-bit byte count, and the third provides the starting page address for the packet. Note that at page 31 of the
transmit buffer, the next consecutive page is page (n). The CPU issues a transmit request to the BCU, which then
communicates this request to the MAC. Once started, the BCU reads data from transmit buffer memory and feeds
the data to the MAC for presentation on the MII. This process continues until the transaction is complete or the
transmission is aborted. The BCU then writes a transmit status word back to transmit buffer memory and notifies
the CPU by setting the interrupt flag. Transmit buffer management should be handled by the application code.
Command/Status (CSR) Registers
The CSR registers are essential in defining the operational characteristics of the Ethernet controller. The CSR
registers contain the following key items:
MAC physical address
Transmit, receive, and flow control settings for the MAC
Multicast hash table used by the address check block
Filter mode and good/bad frame controls for the address check block
VLAN tag identifiers
Wake-up frame filter
Register interface for serial MII PHY management bus
Each CSR register is 32-bits wide and is accessible using the BCUC, CSRA, CSRD SFR interface described in the
Buffer Control Unit section. To program a CSR register, the application code must provide data (CSRD) and
address (CSRA) for the target register before issuing the ‘Write CSR Register’ command to the BCU. When
performing a CSR register read, the application code provides the address (CSRA), issues the ‘Read CSR
Register’ command to the BCU, and then may unload the data (CSRD). The sequences below illustrate the correct
procedures for writing and reading the CSR registers.
CSR Register Write
Load CSRD with MSB of 32-bit word to be written.
Load CSRD with LSB + 2 of the 32-bit word to be written.
Load CSRD with LSB + 1 of the 32-bit word to be written.
Load CSRD with LSB of the 32-bit word to be written.
Load CSRA with address of the CSR register to be written.
Issue the ‘Write CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1000b.
CSR Register Read
Load CSRA with address of the CSR register to be read.
Issue the ‘Read CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1001b.
Wait until the BCU busy bit (BCUC.7) = 0.
Unload CSRD for the MSB of the 32-bit word.
Unload CSRD for the LSB + 2 of the 32-bit word.
Unload CSRD for the LSB + 1 of the 32-bit word.
Unload CSRD for the LSB of the 32-bit word.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS80C410-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C411 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C411-FNY | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C411-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80CH11 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:System Energy Manager |
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