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| 型號： | DS80C410-FNY+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 73/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 90 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 75MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
72 of 102
Ethernet Interrupts
The DS80C410 Ethernet controller supports two interrupt sources: Ethernet power-mode interrupt and the Ethernet
activity interrupt. Each interrupt source has its own enable, priority, and flag bits. The locations of these bits are
documented in the interrupt vector table later in the data sheet (Table 26). Both interrupt sources are globally
enabled or disabled by the EA bit in the IE SFR and both require that the interrupt flags be manually cleared by
application software. The Ethernet power-mode interrupt source, if enabled, can be generated on the reception of a
Magic Packet or network wake-up frame while the Ethernet controller is in sleep mode. The Ethernet activity
interrupt can be triggered when the BCU reports the status of either a transmit or receive packet.
Power Management Block
The DS80C410 Ethernet controller contains a power management block that allows it to be put into a sleep mode
by the CPU, thus conserving power when not actively handling Ethernet traffic.
Sleep mode can be invoked in two different ways. The CPU can issue the ‘Enable Sleep Mode’ command to the
BCU by simply writing the BCUC SFR = 1100b. Alternatively, the Ethernet controller is put into sleep mode when
one or both of the possible wake-up frame sources are enabled. The enable bits for these two wake-up sources,
network wake-up frame and Magic Packet frame, are located in the CSR wake-up frame control and status register
(2Ch). If the network wake-up frame is intended as a wake-up source, the CSR wake-up frame filter register (28h)
should be programmed accordingly prior to invoking sleep mode.
If sleep mode is invoked using the ‘Enable Sleep Mode’ command, the Ethernet controller can be awakened by the
‘Disable Sleep Mode’ command or by either of the two special wake-up frames. If sleep mode is invoked by
enabling one or both wake-up frame sources, only the enabled wake-up frame(s) can remove the condition. To
resume normal Ethernet operation, all enable bits and flag bits (including EPMF of the BCUC SFR) should be
cleared and if the ‘Enable Sleep Mode’ command was used to invoke sleep mode, then the ‘Disable Sleep Mode’
command must be issued.
Magic Packet and Network Wake-Up Frame
The power management block recognizes two types of frames, Magic Packet and network wake-up frame, as
capable of awakening the Ethernet controller from sleep mode. In order for either type of frame to serve as a wake-
up source, it must be programmed to do so.
A Magic Packet is an error-free frame that passes the current destination address filter and that, anywhere after the
source address, contains a data sequence of FFFF_FFFF_FFFFh immediately followed by 16 iterations of the
MAC physical address. When a Magic Packet is detected by the power management block, the Magic Packet-
received bit (bit 5 of CSR wake-up events control and status register) is set, and an interrupt request to the CPU is
generated if enabled (EPMI = 1).
A network wake-up frame is one that passes any of the four user-defined frame filters that have been programmed
into the CSR wake-up frame filter register (28h) and passes the destination address filter (if GU = 0). Each filter is
composed of a command, an offset, a byte mask, and a CRC. The command nibble contains a bit (MSB of
command) to select whether unicast (= 0) or multicast (= 1) frames are to be checked and a bit (LSB of command)
used to disable (= 0) or enable (= 1) that individual frame filter. The offset defines the location of the first byte to be
checked in each potential wake-up frame. Since the destination address is checked by the address check block,
the offset should always be greater than 12. The byte mask is used to define which of the 31 bytes, beginning at
the offset, are to be used for the CRC calculation. Bit 31 of the byte mask is always 0, but for each bit j of the byte
mask that is set to a logic 1, byte (offset + j) is included in the CRC-16 calculation. The CRC contains the CRC-16
of the pattern bytes needed to cause a wake-up event. When a network wake-up frame is recognized, the wake-up
frame received bit (bit 6 of CSR wake-up events control and status register) becomes set and an interrupt request
to the CPU is generated if enabled (EPMI = 1). The wake-up frame-filter register structure is shown in Figure 12.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80C410-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C411 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C411-FNY | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C411-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80CH11 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:System Energy Manager |
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