參數(shù)資料
型號(hào)： DSP101
英文描述： DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
中文描述： DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 12/22頁(yè)
文件大?。?/td> 252K
代理商： DSP101
DSP101/102
12
When a convert command is received, the DSP101 or
DSP102 immediately switches the sampling capacitors to
the hold state, and then internally gates the conversion clock
to the A/D appropriately. Allowing a minimum of 24 CLKIN
pulses between conversions insures that there is sufficient
time for complete, accurate conversions, and allows the
input sampling capacitor to fully acquire the next sample,
regardless of the timing between the convert command and
CLKIN.
In most applications, CLKIN (pin 10) can be driven from a
50% duty cycle clock without performance degradation.
During characterization of the DSP101 and DSP102, the
performance of a number of parts was measured under
various conditions with a 4.8MHz, 50% duty cycle input to
CLKIN at a full 200kHz conversion rate without noticeable
degradation.
OSCILLATOR INPUTS AND CLKOUT
The DSP101 or DSP102 can generate a 33% duty cycle
conversion clock output on CLKOUT (pin 11). This is
accomplished by dividing by three a clock from either an
external 74HC-level clock or from a crystal oscillator.
CLKOUT can deliver
±
2mA, and can be used to drive
multiple DSP101 or DSP102 CLKINs. See Figure 1 for the
timing relationship between OSC1 and CLKOUT.
To use an external 74HC-level clock, drive the clock into
OSC1 (pin 13), and leave OSC2 (pin 14) unconnected.
To use a crystal oscillator to generate the conversion clock,
refer to Figure 5. Connect the oscillator between OSC1 and
OSC2. OSC2 provides the drive for the crystal oscillator.
This pin cannot be used elsewhere in the system.
FIGURE 7. DSP101 or DSP102 Input Buffering.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10μF
10μF
0.1μF
+
VPOTA
VINA
REF
VPOTB
VINB
150
220pF
+
–
7
5
6
1/2
OPA2604
Analog
Input B
150
+
–
1/2
OPA2604
1
Analog
Input A
2.2μF
2.2μF
–5V
+5V
3
2
4
8
220pF
DSP101 or DSP102
(1)
+
+
+
Leave out on DSP101
(1)
NOTE: (1) On DSP101, pin 25 is not internally
connected. Pin 26 must still be bypassed with
the 10μF Tantalum capacitor.
If CLKOUT is not used, both it and OSC2 should be left
unconnected, and OSC1 should be grounded.
TAG FEATURE
Figure 4 shows the implementation of the TAG feature on
the DSP101 and DSP102. When a convert command is
received, the internal Shift/Load signal loads conversion
result data into the output shift register synchronous to
XCLK. Between convert commands, the information input
on TAG (on the DSP101) or on TAGA and TAGB (on the
DSP102) will be clocked into the output shift register on the
rising edges of XCLK. Since this is an 18-bit shift register,
the data input on the Tag lines will be output on SOUT
(DSP101) or SOUTA and SOUTB (DSP102) delayed by 18
bit clocks.
The Tag Feature can be used in various ways. The Tag
inputs can be tied HIGH or LOW to differentiate between
two converters in a system. As discussed in the Applications
section below, the Tag feature can be used to append to the
serial output data word information on multiplexer channel
address, or other digital data related to the input signal (such
as the setting on a programmable gain amplifier.) Another
option would be to daisy-chain multiple DSP101 or DSP102
converters, linking the serial output of one to the Tag input
of the next. This can simplify the transmission of data from
multiple A/Ds over a single optical isolation channel.
DSP102 CASCADE MODE
If pin 22 (CASC) is tied HIGH, the DSP102 will be in the
Cascade Mode. In this mode, when a convert command is
received, the DSP102 will transmit a 32-bit data word on pin
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DSP101/DSP102 制造商:BB 制造商全稱:BB 功能描述:DSP101. DSP102 - DSP-Compatible Sampling Single
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DSP10-12 制造商:TDK-Lambda Corporation 功能描述:Switch Mode Power Supply
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