參數(shù)資料
型號(hào)： DSP101
英文描述： DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
中文描述： DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/22頁(yè)
文件大?。?/td> 252K
代理商： DSP101
DSP101/102
9
The convert command at pin 21 causes a Sync pulse to be
output on pin 15, followed by the data from the previous
conversion output on pin 20. The Sync pulse will be HIGH
for one bit clock cycle, since pin 12 is tied HIGH. (A LOW
Sync pulse will be output on pin 15 if pin 12 is tied LOW.)
Data is serially transmitted in an MSB-first data stream, in
Binary Two’s Complement format. Both the Sync pulse (pin
15) and the data stream (pin 20) are synchronized to the bit
clock (at pins 13 and 16), with the timing relationships
shown in Figure 1.
After the 18 bits of data from the previous conversion have
been transmitted, pin 20 will continue to clock out LOWs
until a new convert command restarts the process, since pin
18 (the Tag input) is grounded. If pin 18 is tied HIGH, pin
20 will clock out HIGHs between conversion cycles.
CONVERSION
A falling edge on pin 21 (CONV) puts the internal sampling
capacitors in the hold state with minimum aperture jitter,
initiates a conversion synchronized to the conversion clock,
and outputs the data from the previous conversion with an
appropriate Sync pulse. On the DSP102, a single convert
command simultaneously samples both channels. The tim-
ing relationship between the convert command, Sync and
the output data is shown in Figure 1. Both Sync and the
output data are synchronized to XCLK, the system bit clock.
Following a convert command falling edge, pin 21 must be
held LOW at least 50ns.
Convert commands can be sent to the DSP101 and DSP102
completely asynchronous to other clocks in the system. This
allows external events to be used to trigger conversions.
From Figure 1, it can be seen that two different clocking
conditions must be considered in determining the minimum
acceptable time between convert commands. First, there
need to be a minimum of 24 XCLK periods between convert
commands, to allow internal synchronization and transmis-
sion of Sync and the data. (In the Cascade Mode on the
DSP102, there need to be at least 40 XCLK periods between
convert commands, to allow transmission of the 32-bit data
words.) When used with DSP processors programmed for
data words longer than 16 bits, the transmission time to the
processor may determine the minimum time between con-
vert commands.
The second limitation on convert commands is the require-
ment that the internal analog-to-digital converter be given
enough time to complete a conversion, shift the data to the
output register, and acquire a new sample. This condition is
met by having a minimum of 24 CLKIN periods between
convert commands, or a minimum of 72 clock cycles on
OSC1, if it is used to generate the conversion clock (CLKOUT
driving CLKIN).
SIGNAL ACQUISITION
After a conversion is completed, the DSP101 or DSP102
will switch back to the sampling mode. With at least 24
CLKIN periods between convert commands, the A/D will
have had sufficient time to acquire a new input sample to full
rated accuracy.
DATA FORMAT AND INPUT LEVELS
The DSP101 and DSP102 output serial data, MSB first, in
Binary Two’s Complement format. In the Cascade Mode on
the DSP102, the serial data will first contain 16 bits of data
for channel A, MSB-first, followed by channel B data, again
MSB-first. The analog input levels that generate specific
output codes are shown in Table I.
As with all standard A/Ds, the first output transition will
occur at an analog input voltage 1/2 LSB above negative full
scale (–2.75V + 1/2 LSB) and the last transition will occur
3/2 LSB below positive full scale (+2.75V – 3/2 LSB.) See
Figure 3.
1FFFF
H
1FFFE
H
00001
00000
H
3FFFF
H
20001
H
20000
H
D
0.00V
+2.749979V
–20.98μV
–2.75V
H
FIGURE 3. Analog Input to Digital Output Diagram.
DIGITAL OUTPUT
(BINARY TWO’S COMPLEMENT)
16-BIT
WORDS
(HEX)
18-BIT
WORDS
(HEX)
ANALOG
INPUT
DESCRIPTION
BINARY CODE
Least Significant Bit
n
(LSB = 2
16-bit Words
18-bit Words
84
μ
V
21
μ
V
Input Range
±
2.75V
+ Full Scale
(2.75V–1LSB)
+2.749916V
+2.749979V
7FFF
1FFFF
Bipolar Zero
(Midscale)
One LSB below
Bipolar Zero
–84
μ
V
–21
μ
V
FFFF
3FFFF
– Full Scale
–2.75V
100…000
8000
20000
TABLE I. Ideal Input Voltage vs Output Code.
0V
000…000
0000
00000
011…111
111…111
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