- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376998 > DSP101 DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS PDF資料下載
參數(shù)資料
| 型號： | DSP101 |
| 英文描述： | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 252K |
| 代理商： | DSP101 |
DSP101/102
16
of the MSB capacitor in the CDAC. These pins are nomi-
nally at +100mV after laser-trimming during manufacturing.
They can handle external inputs up to about one diode drop
below ground (–0.6V) before internal clamping circuitry is
triggered.
Figure 8 shows an appropriate circuit for adjusting the
weight of the most significant bit to minimize differential
non-linearity at the critical major-carry transition. To adjust,
provide a small amplitude sine wave to the selected A/D
input pin while converting continually, and adjust for maxi-
mum Signal-to-(Noise + Distortion) ratio, using appropriate
signal analysis software.
GAIN ADJUST
If circuit gain needs to be adjusted in hardware, rather than
in system software, appropriate trimpots should be included
in the analog signal conditioning section in front of the
DSP101 or DSP102. No specific gain adjust circuitry is
included in the parts.
APPLICATIONS
INTERFACING DSP101 TO PARALLEL PORTS
Figure 9 shows a circuit for converting the serial output data
from the DSP101 into 16 bits of parallel data, within the
timing constraints of the serial bit-stream from the DSP101.
In many applications, this circuit can be easily incorporated
into gate arrays or other programmed logic circuits already
used in the system, since the extra gate count is not high.
This circuit adds an additional pipeline delay to the conver-
sion data, so that the parallel data from a conversion at time
(t) is valid one conversion cycle plus 17 XCLK clocks later
(at t+1 plus 17 times XCLK). A convert command at time
(t+1) generates a Sync and begins transmitting serial data
from SOUT. The serial data is shifted into the 74HC594
shift registers, and Sync is shifted through the 74HC164
shift registers. The Q1 output of the 74HC74 dual D-type
flip-flops clocks the conversion data into the output register
of the 74HC594s, and triggers a data valid signal on its Q2
output. The user can then read the data at any time before the
next conversion is started, and the Read signal will reset the
data valid output from Q2.
In many systems, galvanic isolation of signals is required.
Using opto-couplers on the serial data lines in Figure 9
allows a fully isolated system to be built using a DSP101 and
only three couplers across the barrier (for serial data, XCLK
and SYNC.)
MULTIPLEXING INPUTS TO THE DSP101
Figure 10 shows a complete circuit for sequentially scanning
eight analog input channels with a single DSP101, and using
the Tag feature on the DSP101 to append the multiplexer
channel address to the serial output conversion results.
The circuit in Figure 10 includes the required digital logic
and timing logic. The 74HC163 counter provides the scan
sequence to the Burr-Brown HI-508A analog multiplexer. In
order to allow the HI-508A enough time to switch to the next
channel and settle before the DSP101 begins a conversion,
a 74HC221 one-shot introduces a 3
μ
s delay for the DSP101
convert command input.
The Burr-Brown OPA627 provides a low impedance source
for the DSP101, buffering it from the output impedance of
FIGURE 11. Analog Input and Analog Output System.
TTL Bit
Clock
12
13
11
9
10
15
XCLK
SIN
SYNC
SSF
SWL
CONV
±3V Analog Output
21
VOUT
DSP201
Conversion Rate
Generator
XCLK
SOUT
SYNC
SSF
DSP101
SSF
SWL
16
20
15
12
2
±2.75V
Analog Input
CLKR
DATA IN
SYNC
XCLK
DATA OUT
SYNC
SSF
(2)
VIN
Digital Signal
Processor IC
21
CONV
(1)
(2)
(3)
DSP PROCESSOR
SYNC FORMAT
SERIAL I/O WORD
SSF
(2)
SWL
(3)
DSP32C, DSP16
DSP56001
DSP56001
TMS320C25/C30
ADSP2101/2105
Active Low
Active High
Active High
Active High
Active High
16 Bits
24 Bits
16 Bits
16 Bits
16 Bits
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
(1) See Burr-Brown
DSP201/DSP202
product data sheet
for full description of
this DAC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP101JP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP101KP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP102JP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP102KP | TVS 400W 6.0V UNIDIRECT SMA |
| DSP10 | Power Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP101/DSP102 | 制造商:BB 制造商全稱:BB 功能描述:DSP101. DSP102 - DSP-Compatible Sampling Single |
| DSP101_05 | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP1012 | 制造商:TDK-Lambda Corporation 功能描述:AC/DC Power Supply Single-OUT 12V 0.83A 10W 制造商:TDK-Lambda Corporation 功能描述:AC/DC PS SGL-OUT 12V 0.83A 10W - Bulk 制造商:TDK 功能描述:PWR SUP DIN RAIL 12V 10.0W .83A |
| DSP10-12 | 功能描述:DIN導(dǎo)軌式電源 10W 12V 0.83A DIN Rail 115-230VAC RoHS:否 制造商:Mean Well 產(chǎn)品:Linear Supplies 商用/醫(yī)用:Commercial 輸出功率額定值:960 W 輸入電壓:180 VAC to 264 VAC, 254 VDC to 370 VDC 輸出端數(shù)量:1 輸出電壓（通道 1）:48 V 輸出電流（通道 1）: 輸出電壓（通道 2）: 輸出電流（通道 2）: 輸出電壓（通道 3）: 輸出電流（通道 3）: 尺寸:150 mm L x 110 mm W |
| DSP10-12 | 制造商:TDK-Lambda Corporation 功能描述:Switch Mode Power Supply |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。