參數(shù)資料
型號(hào): DSP101
英文描述: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
中文描述: DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 14/22頁
文件大?。?/td> 252K
代理商: DSP101
DSP101/102
14
Optimal dynamic performance is achieved by soldering the
parts directly into boards, to keep the A/Ds as close as
possible to ground. The use of sockets will often degrade AC
performance. Zero-Insertion-Force sockets are particularly
poor because longer lead lengths create inductance.
Short traces on the board, and bypass capacitors as close as
possible to the A/D, will further improve dynamic perfor-
mance.
GROUNDS
To achieve the maximum performance from the DSP101 or
DSP102, care should be taken to minimize the effect of
changes in current flowing in the system grounds, particu-
larly while bit decisions are being made in the successive
approximation converter’s comparator. Pin 28 (AGND) on
both the DSP101 and the DSP102 is the most critical, and
care should be taken to make this pin as close as possible to
the same potential as the system analog ground.
Whenever possible, it is strongly recommended that separate
analog and digital ground planes be used. With an LSB level
of 84
μ
V at the 16-bit level, and one-quarter of that at the
18-bit level, the currents switched in a typical DSP system
can easily corrupt the accuracy of the A/Ds unless great care
is taken to analyze and design for current flows.
FIGURE 9. Driving a 16-bit Parallel Port from the DSP101.
TTL Bit
Clock
20
12
Serial Data
74HC594
(1)
DSP101
SOUT
SSF
XCLK
SR CLK
QH
SR CLR
R CLR
10
13
15
1
2
3
4
5
6
7
12
SYNC
D15 (LSB)
D14
D13
D12
D11
D10
D9
D8
QH
RCK
QA
D1
74HC164
D2
CLR
Serial Data
74HC594
(1)
SR CLK
SR CLR
R CLR
10
13
11
15
1
2
3
4
5
6
7
12
D7
D6
D5
D4
D3
D2
D1
D0 (MSB)
QH
RCK
QA
+5V
+5V
8
13
1
2
9
CLK
Q7
15
D1
74HC164
D2
CLR
CLK1
D1
S1
R1
D2
S2
R2
74HC74
5
11
9
CLK2
Q2
Q1
+5V
+5V
8
13
1
2
9
CLK
Q7
4
1
12
10
13
+5V
RD
Data Valid Signal
NOTE: (1) Substituting
74HC595s provides three
state outputs, with pin 13 (OE)
used to enable the parallel
data lines.
+5V
+5V
2
3
14
11
9
14
16
+5V
HC04
POWER SUPPLY DECOUPLING
All of the supplies should be decoupled to the appropriate
grounds using tantalum capacitors in parallel with ceramic
capacitors, as shown in Figure 6. For optimum performance
of any high resolution A/D, all of the supplies should be as
clean as possible. If separate digital and analog supplies are
available in a system, care should be taken to insure that the
difference between the analog and the digital supplies is not
more than 0.5V for more than a few hundred milliseconds,
as may occur at power-on.
INPUT SIGNAL CONDITIONING
To avoid introducing distortion, the DSP101 and DSP102
analog inputs must be driven by a source with low imped-
ance over the input bandwidth needed in the application. Op
amps such as the NE5532 or Burr-Brown’s OPA2604 work
well over audio bandwidths. Figure 7 shows an appropriate
input driver circuit. The 150
and 220pF shown on the input
help reduce the dynamic load on the input signal condition-
ing amp in front of the A/D, since all switched capacitor
array architectures exhibit fast changes in input current load
as the input sampling switch is opened and closed. These
dynamic changes in the load can affect any signal condition-
ing circuit at the input. Other R and C combinations can be
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DSP101/DSP102 制造商:BB 制造商全稱:BB 功能描述:DSP101. DSP102 - DSP-Compatible Sampling Single
DSP101_05 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
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DSP10-12 功能描述:DIN導(dǎo)軌式電源 10W 12V 0.83A DIN Rail 115-230VAC RoHS:否 制造商:Mean Well 產(chǎn)品:Linear Supplies 商用/醫(yī)用:Commercial 輸出功率額定值:960 W 輸入電壓:180 VAC to 264 VAC, 254 VDC to 370 VDC 輸出端數(shù)量:1 輸出電壓(通道 1):48 V 輸出電流(通道 1): 輸出電壓(通道 2): 輸出電流(通道 2): 輸出電壓(通道 3): 輸出電流(通道 3): 尺寸:150 mm L x 110 mm W
DSP10-12 制造商:TDK-Lambda Corporation 功能描述:Switch Mode Power Supply