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參數(shù)資料
| 型號： | DSP101 |
| 英文描述： | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 252K |
| 代理商： | DSP101 |
DSP101/102
17
the multiplexer. This unity-gain buffer minimizes distortion,
taking full advantage of the resolution and bandwidth of the
DSP101.
The 74HC574D register delays the multiplexer address data
by one conversion before appending the channel data to the
serial conversion results from the DSP101. This attaches the
channel address to the correct conversion results. Since the
channel scanning shown in Figure 10 is sequential, this
delay latch could be left out and software could recognize
that the time (t) conversion results have the MUX address
from the time (t-1) conversion appended. However, for
systems using non-sequential scan lists, this delay latch is
essential to maintain the conversion data and channel ad-
dress integrity.
The 74HC166 synchronous loading shift register loads the
channel address tag data into the shift register on the rising
edge of the bit clock, in conjunction with the Sync output of
the DSP101. The channel address tag data is then clocked
into the DSP101 Tag input (pin 18) by the bit clock, while
the conversion data is clocked out the other end of the
DSP101 shift register (discussed in another section of this
data sheet.)
Figure 10 was developed and tested using a Burr-Brown
ZPB34 DSP board, which contains an AT&T DSP32C, so
that the SYNC output is programmed to be active LOW. The
circuit needs to be modified for DSP processors from ADI,
TI, and Motorola, which use active HIGH Sync pulses. For
these processors, tie SSF (pin 12) on the DSP101 HIGH, and
use a 74HC04 hex inverter to invert the Sync signal to the
74HC574 and 74HC166.
The same basic circuit can be duplicated to drive two
channels in a DSP102, or can be easily modified for more or
less than eight channels of analog input.
USING DSP101 AND DSP102 WITH
TEXAS INSTRUMENTS DSP ICS
Figures 11 thru 17 show various ways to use the DSP101
and DSP102 with DSP ICs from the Texas Instruments
TMS320Cxx series. For simplicity, all of these circuits are
FIGURE 13. Using DSP102 with TMS320C30 in Cascade Mode.
16
15
20
17
22
12
21
CLKR -0
FSR-0
DR-0
±2.75V Analog Input
Channel A
±2.75V Analog Input
Channel B
2
25
VINA
VINB
TMS320C30
Conversion Rate
Generator
DSP102
XCLK
SYNC
SOUTA
SOUTB
CASC
SSF
CONV
+5V
+5V
NOTE: Serial port 0 programmed
for 32-bit data.
TTL Bit
Clock
NC
FIGURE 12. Using DSP102 with TMS320C30.
TTL Bit
Clock
16
15
20
17
22
12
21
CLKR
±2.75V Analog Input
Channel A
±2.75V Analog Input
Channel B
2
VINA
VINB
TMS320C30
Conversion Rate
Generator
DSP102
25
XCLK
SYNC
SOUTA
SOUTB
CASC
SSF
CONV
DR-0
DR-1
FSR-0
FSR-1
+5V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP101JP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP101KP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP102JP | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP102KP | TVS 400W 6.0V UNIDIRECT SMA |
| DSP10 | Power Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP101/DSP102 | 制造商:BB 制造商全稱:BB 功能描述:DSP101. DSP102 - DSP-Compatible Sampling Single |
| DSP101_05 | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP1012 | 制造商:TDK-Lambda Corporation 功能描述:AC/DC Power Supply Single-OUT 12V 0.83A 10W 制造商:TDK-Lambda Corporation 功能描述:AC/DC PS SGL-OUT 12V 0.83A 10W - Bulk 制造商:TDK 功能描述:PWR SUP DIN RAIL 12V 10.0W .83A |
| DSP10-12 | 功能描述:DIN導(dǎo)軌式電源 10W 12V 0.83A DIN Rail 115-230VAC RoHS:否 制造商:Mean Well 產(chǎn)品:Linear Supplies 商用/醫(yī)用:Commercial 輸出功率額定值:960 W 輸入電壓:180 VAC to 264 VAC, 254 VDC to 370 VDC 輸出端數(shù)量:1 輸出電壓（通道 1）:48 V 輸出電流（通道 1）: 輸出電壓（通道 2）: 輸出電流（通道 2）: 輸出電壓（通道 3）: 輸出電流（通道 3）: 尺寸:150 mm L x 110 mm W |
| DSP10-12 | 制造商:TDK-Lambda Corporation 功能描述:Switch Mode Power Supply |
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