- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19497 > DSP56321VL275 (Freescale Semiconductor)IC DSP 24BIT 275MHZ 196-MAPBGA PDF資料下載
參數(shù)資料
| 型號： | DSP56321VL275 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 28/84頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 275MHZ 196-MAPBGA |
| 標準包裝： | 126 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 275MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-FBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
DSP56321 Technical Data, Rev. 11
2-14
Freescale Semiconductor
Specifications
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the
reason for timing 250.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other
DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG
is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.
Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251
ensures that overlaps are avoided.
2.4.6
Host Interface Timing
Figure 2-12.
Asynchronous Bus Arbitration Timing
Table 2-10.
Host Interface Timings1,2,12
No.
Characteristic10
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Uni
t
Min
Max
Min
Max
Min
Max
Min
Max
317
Read data strobe assertion width
5
HACK assertion width
TC + 4.95
9.95
—
9.05
—
8.3
—
7.77
—
ns
318
Read data strobe deassertion width5
HACK deassertion width
4.95
—
4.5
—
4.13
—
4.0
—
ns
319
Read data strobe deassertion width5 after
“Last Data Register” reads8,11, or between two
consecutive CVR, ICR, or ISR reads
3
HACK deassertion width after “Last Data
Register” reads8,11
2.5
× T
C + 3.3
15.8
—
14.7
—
13.7
—
12.39
—
ns
320
Write data strobe assertion width
6
6.6
—
6.0
—
5.5
—
5.1
—
ns
321
Write data strobe deassertion width8
HACK write deassertion width
after ICR, CVR and “Last Data Register”
writes
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND=
0), or
after TXL:TXM:TXH writes (with HLEND =
1)
2.5
× TC + 3.3 15.8
8.25
—
14.7
7.5
—
13.7
6.88
—
12.39
6.28
—
ns
322
HAS assertion width
4.95
—
4.5
—
4.13
—
4.0
—
ns
BG1
BB
251
BG2
250
250+251
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCM03DSUN | CONN EDGECARD 6POS .156 DIP SLD |
| GMA50DRST-S288 | CONN EDGECARD 100POS .125 EXTEND |
| ABM36DRST-S288 | CONN EDGECARD EXTEND 72POS .156 |
| ACM28DTAH-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| DSP56321VL240 | IC DSP 24BIT 240MHZ 196-MAPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56321VL275 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC |
| DSP56362 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56362AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56362D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56362EVMUPUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56362EVMUPUM DPSD56362EVM Upgrade Manual Revision 3.1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。