參數(shù)資料
型號(hào)： DSP56321VL275
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 38/84頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 275MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP56K/Symphony
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 275MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-FBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
AC Electrical Characteristics
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-23
2.4.8
ESSI0/ESSI1 Timing
Table 2-12.
ESSI Timings
No.
Characteristics4, 6
Symbol Expression
200 MHz
220 MHz
240 MHz
275 MHz
Cond-
ition5
Unit
Min Max Min Max Min Max Min Max
430 Clock cycle1
TECCX
TECCI
6
× TC
8
× TC
30.0
40.0
—
27.3
36.6
—
25.0
33.3
—
21.5
25.0
—
x ck
i ck
ns
431 Clock high period
For internal clock
For external clock
TECCX/2 – 3.7
TECCI/2 – 10.0
11.3
10.0
—
9.9
8.2
—
8.8
6.7
—
7.21
2.5
—
ns
432 Clock low period
For internal clock
For external clock
TECCX/2 – 3.7
TECCI/2 10.0
11.3
10.0
—
9.9
8.2
—
8.8
6.7
—
7.21
2.5
—
ns
433 RXC rising edge to FSR out (bit-length)
high
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
434 RXC rising edge to FSR out (bit-length)
low
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
435 RXC rising edge to FSR out (word-
length-relative) high
2
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
436 RXC rising edge to FSR out (word-
length-relative) low2
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
437 RXC rising edge to FSR out (word-
length) high
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
438 RXC rising edge to FSR out (word-
length) low
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck a
ns
439 Data in setup time before RXC (SCK in
Synchronous mode) falling edge
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
x ck
i ck
ns
440 Data in hold time after RXC falling edge
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
x ck
i ck
ns
441 FSR input (bl, wr) high before RXC
falling edge
2
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
x ck
i ck a
ns
442 FSR input (wl) high before RXC falling
edge
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
x ck
i ck a
ns
443 FSR input hold time after RXC falling
edge
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
x ck
i ck a
ns
444 Flags input setup before RXC falling
edge
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
5.0
10.0
—
x ck
i ck s
ns
445 Flags input hold time after RXC falling
edge
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
3.8
5.0
—
x ck
i ck s
ns
446 TXC rising edge to FST out (bit-length)
high
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck
ns
447 TXC rising edge to FST out (bit-length)
low
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck
ns
448 TXC rising edge to FST out (word-
length-relative) high2
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck
ns
449 TXC rising edge to FST out (word-
length-relative) low2
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck
ns
450 TXC rising edge to FST out (word-
length) high
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
—
12.5
8.3
x ck
i ck
ns
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