參數(shù)資料
型號: DSP56321VL275
廠商: Freescale Semiconductor
文件頁數(shù): 43/84頁
文件大小: 0K
描述: IC DSP 24BIT 275MHZ 196-MAPBGA
標準包裝: 126
系列: DSP56K/Symphony
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 275MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-FBGA
供應商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤
DSP56321 Technical Data, Rev. 11
2-28
Freescale Semiconductor
Specifications
2.4.11 JTAG Timing
Table 2-14.
JTAG Timing
No.
Characteristics
All frequencies
Unit
Min
Max
500
TCK frequency of operation (1/(T
C ×
3); absolute maximum 22 MHz)
0.0
22.0
MHz
501
TCK cycle time in Crystal mode
45.0
ns
502
TCK clock pulse width measured at 1.6 V
20.0
ns
503
TCK rise and fall times
0.0
3.0
ns
504
Boundary scan input data setup time
5.0
ns
505
Boundary scan input data hold time
24.0
ns
506
TCK low to output data valid
0.0
40.0
ns
507
TCK low to output high impedance
0.0
40.0
ns
508
TMS, TDI data setup time
5.0
ns
509
TMS, TDI data hold time
25.0
ns
510
TCK low to TDO data valid
0.0
44.0
ns
511
TCK low to TDO high impedance
0.0
44.0
ns
512
TRST assert time
100.0
ns
513
TRST setup time to TCK low
40.0
ns
Notes:
1.
VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.
2.
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
Figure 2-28.
Test Clock Input Timing Diagram
TCK
(Input)
VM
VIH
VIL
501
502
503
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