參數(shù)資料
型號： DSP56367UM
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 2/100頁
文件大?。?/td> 1039K
代理商： DSP56367UM
Overview
DSP56367 Technical Data, Rev. 2.1
1-2
Freescale Semiconductor
Figure 1-1 DSP56367 Block Diagram
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted”
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples:
Signal/Symbol
Logic State
Signal State
Voltage*
PIN
True
Asserted
V
IL
/ V
OL
V
IH
/ V
OH
V
IH
/ V
OH
V
IL
/ V
OL
PIN
False
Deasserted
PIN
True
Asserted
PIN
False
Deasserted
Note:
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
CLOCK
GENERATOR
INTERNAL
DATA
BUS
SWITCH
EXTAL
PROGRAM
RAM
/INSTR. CACHE
3K x 24
PROGRAM
ROM
40K x 24
Bootstrap ROM
192 x 24
PROGRAM
INTERRUPT
CONTROLLER
PROGRAM
DECODE
CONTROLLE
PROGRAM
ADDRESS
GENERATOR
YAB
XAB
PAB
DAB
YDB
XDB
PDB
GDB
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
DATA ALU
24X24+56->56-BIT MAC
TWO 56-BIT ACCUMULATORS
BARREL SHIFTER
PLL
OnCE
HOST
INTER-
FACE
DAX
(SPDIF Tx.)
INTERFACE
4
16
X
MEMORY
RAM
13K X 24
ROM
32K x 24
Y
MEMORY
RAM
7K X 24
ROM
8K x 24
DDB
SIX CHANNELS
DMA UNIT
MEMORY EXPANSION AREA
PERIPHERAL
EXPANSION AREA
Y
X
P
P
24 BITS BUS
JTAG
4
5
RESET
PINIT/NMI
POWER
MNGMNT
2
TRIPLE
TIMER
1
DRAM &
SRAM BUS
INTERFACE
&
I - CACHE
EXTERNAL
ADDRESS
BUS
SWITCH
EXTERNAL
DATA BUS
SWITCH
ADDRESS
10
DATA
CONTROL
24
18
ESAI
INTER-
FACE
8
6
ESAI_1
ADDRESS
GENERATION
UNIT
24-BIT
DSP56300
Core
SHI
INTER-
FACE
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