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參數資料
| 型號： | DSP56367UM |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數字信號處理器 |
| 文件頁數： | 28/100頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | DSP56367UM |
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AC Electrical Characteristics
DSP56367 Technical Data, Rev. 2.1
3-4
Freescale Semiconductor
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
IL
maximum
of 0.4 V and a V
IH
minimum of 2.4 V for all pins except EXTAL. AC timing specifications, which are
referenced to a device input signal, are measured in production with respect to the 50% point of the
respective input signal’s transition. DSP56367 output levels are measured with the production test machine
V
OL
and V
OH
reference levels set at 0.4 V and 2.4 V, respectively.
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz, the
device AC test conditions are 15 MHz and rated speed.
3.6
Internal Clocks
3
This characteristic does not apply to PCAP.
4
The
Appendix A, "Power Consumption Benchmark"
section provides a formula to compute the estimated current
requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float).
Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are
90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is
measured with V
CCQL
= 1.8V, V
CC(other)
= 3.3V at T
J
= 25°C. Maximum internal supply current is measured with V
CCQL
= 1.89V,
V
CC(other)
= 3.46V at T
J
= 95°C.
5
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to
float).
6
Periodically sampled and not 100% tested
Table 3-4 Internal Clocks
Characteristics
Symbol
Expression
1, 2
Min
Typ
Max
Internal operation frequency with PLL enabled
f
—
(Ef
×
MF)/(PDF
×
DF)
—
Internal operation frequency with PLL disabled
f
—
Ef/2
—
Internal clock high period
With PLL disabled
With PLL enabled and MF
≤
4
With PLL enabled and MF > 4
T
H
—
0.49
×
ET
C
×
PDF
×
DF/MF
0.47
×
ET
C
×
PDF
×
DF/MF
ET
C
—
—
—
0.51
×
ET
C
×
PDF
×
DF/MF
0.53
×
ET
C
×
PDF
×
DF/MF
Internal clock low period
With PLL disabled
With PLL enabled and MF
≤
4
With PLL enabled and MF > 4
T
L
—
0.49
×
ET
C
×
PDF
×
DF/MF
0.47
×
ET
C
×
PDF
×
DF/MF
ET
C
—
—
—
0.51
×
ET
C
×
PDF
×
DF/MF
0.53
×
ET
C
×
PDF
×
DF/MF
Internal clock cycle time with PLL enabled
T
C
—
ET
C
×
PDF
×
DF/MF
—
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