參數(shù)資料
型號: DSP56857BUE
廠商: Freescale Semiconductor
文件頁數(shù): 15/53頁
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 100-LQFP
標準包裝: 90
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: SCI,SPI,SSI
外圍設備: DMA,POR,WDT
輸入/輸出數(shù): 47
程序存儲器容量: 80KB(40K x 16)
程序存儲器類型: SRAM
RAM 容量: 24K x 16
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
56857 Technical Data, Rev. 6
22
Freescale Semiconductor
Table 4-1 Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage, core
VDD1
1. VDD must not exceed VDDIO
VSS – 0.3
VSS + 2.0
V
Supply voltage, IO
Supply voltage, analog
VDDIO2
2. VDDIO and VDDA must not differ by more that 0.5V
VSSIO – 0.3
VSSA – 0.3
VSSIO + 4.0
VDDA + 4.0
V
Digital input voltages
Analog input voltages (XTAL, EXTAL)
VIN
VINA
VSSIO – 0.3
VSSA – 0.3
VSSIO + 5.5
VDDA + 0.3
V
Current drain per pin excluding VDD, GND
I
8
mA
Junction temperature
TJ
-40
120
°C
Storage temperature range
TSTG
-55
150
°C
Table 4-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
Supply voltage for Logic Power
VDD
1.62
1.98
V
Supply voltage for I/O Power
VDDIO
3.0
3.6
V
Supply voltage for Analog Power
VDDA
3.0
3.6
V
Ambient operating temperature
TA
-40
85
°C
PLL clock frequency1
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
fpll
—240
MHz
Operating Frequency2
2. Master clock is derived from on of the following four sources:
fclk = fxtal when the source clock is the direct clock to EXTAL
fclk = fpll when PLL is selected
fclk = fosc when the source clock is the crystal oscillator and PLL is not selected
fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected
fop
—120
MHz
Frequency of peripheral bus
fipb
—60
MHz
Frequency of external clock
fclk
—240
MHz
Frequency of oscillator
fosc
24
MHz
Frequency of clock via XTAL
fxtal
—240
MHz
Frequency of clock via EXTAL
fextal
24
MHz
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