參數(shù)資料
型號(hào)： DSP56857BUE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 44/53頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 47
程序存儲(chǔ)器容量： 80KB（40K x 16）
程序存儲(chǔ)器類(lèi)型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
Electrical Design Considerations
56857 Technical Data, Rev. 6
Freescale Semiconductor
49
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,
the new thermal metric, Thermal Characterization Parameter, or
ΨJT, has been defined to be (TJ – TT)/PD.
This value gives a better estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
6.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
The minimum bypass requirement is to place six 0.01–0.1
μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the ten VDD/VSS pairs, including VDDA/VSSA.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.
Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
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