參數(shù)資料
型號： DSP56857BUE
廠商： Freescale Semiconductor
文件頁數(shù)： 22/53頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 100-LQFP
標準包裝： 90
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 47
程序存儲器容量： 80KB（40K x 16）
程序存儲器類型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56857 Technical Data, Rev. 6
Freescale Semiconductor
29
4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-6 PLL Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
fosc
24
4
MHz
PLL output frequency
fclk
40
—
240
MHz
PLL stabilization time 2
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
tplls
—1
10
ms
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typ Min
Typ
Max
Unit
See Figure
Minimum RESET Assertion Duration3
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,
txtal, textal or tosc.
tRA
30
—
ns
Edge-sensitive Interrupt Request Width
tIRW
1T + 3
—
ns
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
18T
—
ns
IRQA Width Assertion to Recover from Stop State
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)4
Fast5
Normal6, 7
4. This interrupt instruction fetch is visible on the pins only in Mode 3.
5. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is request-
ed (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less
cycle and tclk will continue with the same value it had before stop mode was entered.
6. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
tIF
—
13T
25ET
ns
RSTO pulse width7
normal operation
internal reset mode
7. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.
tRSTO
128ET
8ET
—
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