參數(shù)資料
型號： DSP56857BUE
廠商： Freescale Semiconductor
文件頁數(shù)： 7/53頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 47
程序存儲器容量： 80KB（40K x 16）
程序存儲器類型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
Introduction
56857 Technical Data, Rev. 6
Freescale Semiconductor
15
77
TIO3
GPIOG3
Input/Output
Input/Output
Timer Input/Output (TIO3)—This pin can be independently configured to
be either a timer input source or an output flag.
Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
15
IRQA
Input
External Interrupt Request A and B—The IRQA and IRQB inputs are
asynchronous external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for Wired-OR operation.
16
IRQB
10
MODE A
GPIOH0
Input
Input/Output
Mode Select (MODE A)—During the bootstrap process MODE A selects
one of the eight bootstrap modes.
Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
11
MODE B
GPIOH1
Input
Input/Output
Mode Select (MODE B)—During the bootstrap process MODE B selects
one of the eight bootstrap modes.
Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
12
MODE C
GPIOH2
Input
Input/Output
Mode Select (MODE C)—During the bootstrap process MODE C selects
one of the eight bootstrap modes.
Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
28
RESET
Input
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is latched
from the MODE A, MODE B, and MODE C pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not to
reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but
do not assert TRST.
27
RSTO
Output
Reset Output (RSTO)—This output is asserted on any reset condition
(external reset, low voltage, software or COP).
51
RXD0
GPIOE0
Input
Input/Output
Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial
data and transfers it to the SCI 0 receive shift register.
Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
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