56854 Technical Data, Rev. 6
14
Freescale Semiconductor
77
CS2
GPIOA2
Output
Input
/Output
External Chip Select (CS2)
—This pin is used as a dedicated GPIO.
Port A GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
78
CS3
GPIOA3
Output
Input
/Output
External Chip Select (CS3)
—This pin is used as a dedicated GPIO.
Port A GPIO (3)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
30
HD0
GPIOB0
Input
Input/Output
Host Address (HD0)—
This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
31
HD1
GPIOB1
Input
Input/Output
Host Address (HD1)—
This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
32
HD2
GPIOB2
Input
Input/Output
Host Address (HD2)—
This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
36
HD3
GPIOB3
Input
Input/Output
Host Address (HD3)—
This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (3)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
37
HD4
GPIOB4
Input
Input/Output
Host Address (HD4)—
This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (4)
—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description