參數(shù)資料
型號(hào)： DSP5685xUM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 34/60頁(yè)
文件大?。?/td> 836K
代理商： DSP5685XUM
56854 Technical Data, Rev. 6
34
Freescale Semiconductor
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
RD Deasserted to Address Invalid
t
RDA
- 0.44
0.00
RWSH
ns
Address Valid to RD Deasserted
t
ARDD
-2.07
1.00
RWSS,RWS
ns
Valid Input Data Hold after RD
Deasserted
t
DRD
0.00
N/A
1
—
ns
RD Assertion Width
t
RD
-1.34
1.00
RWS
ns
Address Valid to Input Data Valid
t
AD
-10.27
1.00
RWSS,RWS
ns
-13.5
1.19
Address Valid to RD Asserted
t
ARDA
- 0.94
0.00
RWSS
ns
RD Asserted to Input Data Valid
t
RDD
-9.53
1.00
RWSS,RWS
ns
-12.64
1.19
WR Deasserted to RD Asserted
t
WRRD
-0.75
0.25
WWSH,RWSS
ns
RD Deasserted to RD Asserted
t
RDRD
-0.16
2
0.00
RWSS,RWSH
ns
WR Deasserted to WR Asserted
t
WRWR
WWS=0
-0.44
0.75
WWSS, WWSH
ns
WWS>0
-0.11
1.00
RD Deasserted to WR Asserted
t
RDWR
0.14
0.50
MDAR, BMDAR,
RWSH, WWSS
ns
-0.57
0.69
1.
2.
N/A since device captures data before it deasserts RD
If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
11
ns
4-12
Minimum RESET Assertion Duration
3
t
RA
30
—
ns
4-12
RESET Deassertion to First External Address Output
t
RDA
—
120T
ns
4-12
Edge-sensitive Interrupt Request Width
t
IRW
1T + 3
—
ns
4-13
Figure 4-11 External Memory Interface Timing (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98 V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
< 50pF, P = 8.333ns
Characteristic
Symbol
Wait States
Configuration
D
M
Wait States
Controls
Unit
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