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| 型號： | DSP5685xUM |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 836K |
| 代理商： | DSP5685XUM |
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56854 Technical Data, Rev. 6
32
Freescale Semiconductor
4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices.
Figure 4-10
shows
sample timing and parameters that are detailed in
Table 4-11
.
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
t
parameter delay time
D
fixed portion of the delay, due to on-chip path delays.
P
the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
clock duty cycle derating.
W the sum of the applicable wait state controls. See the “Wait State Controls” column of
Table 4-11
for
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of
Table 4-11
should
be used to make the appropriate selection.
Table 4-6 PLL Timing
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
The PLL is optimized for 4MHz input crystal.
2.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
f
osc
2
4
4
MHz
PLL output frequency
f
clk
40
—
240
MHz
PLL stabilization time
2
t
plls
—
1
10
ms
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