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參數(shù)資料
| 型號： | DSP56F801 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數(shù)： | 15/44頁 |
| 文件大小： | 858K |
| 代理商： | DSP56F801 |
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DC Electrical Characteristics
56F801 Technical Data
15
PWM pin output sink current
5
I
OLP
16
—
—
mA
Input capacitance
C
IN
—
8
—
pF
Output capacitance
C
OUT
—
12
—
pF
V
DD
supply current
I
DDT6
Run
7
(80MHz operation)
—
120
130
mA
Run
7
(60MHz operation)
—
102
111
mA
Wait
8
—
96
102
mA
Stop
—
62
70
mA
Low Voltage Interrupt, external power supply
9
V
EIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply
10
V
EIC
2.0
2.2
2.4
V
Power on Reset
11
V
POR
—
1.7
2.0
V
1.
2.
3.
4.
5.
6.
7.
configured as inputs; measured with all modules enabled.
8.
Wait I
DD
measured using external square wave clock source (f
osc
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC
loads; less than 50pF on all outputs. C
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects
wait I
DD
; measured with PLL enabled.
9.
This low voltage interrupt monitors the V
DDA
external power supply. V
DDA
is generally connected to the same potential
as V
DD
via separate traces. If V
DDA
drops below V
EIO
, an interrupt is generated. Functionality of the device is guaranteed
under transient conditions when V
DDA
>V
EIO
(between the minimum specified V
DD
and the point when the V
EIO
interrupt is
generated).
10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is
regulator drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not
be generated unless the external power supply drops below the minimum specified value (3.0V).
11. Power
–
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up
rate is. The internally regulated voltage is typically 100 mV less than V
DD
during ramp up until 2.5V is reached, at which time
it self regulates.
Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
PWM pin output source current measured with 50% duty cycle.
PWM pin output sink current measured with 50% duty cycle.
I
DDT
= I
DD
+ I
DDA
(Total supply current for V
DD
+ V
DDA
)
Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
Table 17. DC Electrical Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| DSP56F803E | 16-bit Digital Signal Controllers |
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| DSP56F805 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F807PY80E | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F801-7UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F801E | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F801 16-bit Hybrid Controller |
| DSP56F801EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F801 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| DSP56F801EVMUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F801 Evaluation Module Hardware User＇s Manual |
| DSP56F801FA60 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60Mhz/30MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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