參數(shù)資料
型號(hào)： DSP56F801
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 25/44頁(yè)
文件大?。?/td> 858K
代理商： DSP56F801
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F801 Technical Data
25
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 24. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
1.
2.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
21
ns
Figure 15
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
t
RA
275,000T
128T
—
—
ns
ns
Figure 15
RESET De-assertion to First External Address
Output
t
RDA
33T
34T
ns
Figure 15
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
Figure 16
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
15T
—
ns
Figure 17
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T
—
ns
Figure 17
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State
3
3.
t
IRI
13T
—
ns
Figure 18
IRQA Width Assertion to Recover from Stop State
4
t
IW
2T
—
ns
Figure 19
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
Figure 19
Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
Figure 20
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
Figure 20
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F801-7UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F801E 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F801 16-bit Hybrid Controller
DSP56F801EVM 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F801 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
DSP56F801EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F801 Evaluation Module Hardware User＇s Manual
DSP56F801FA60 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 60Mhz/30MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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