參數(shù)資料
型號(hào): DSP56F801
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁(yè)數(shù): 5/44頁(yè)
文件大?。?/td> 858K
代理商: DSP56F801
Data Sheet Conventions
56F801 Technical Data
5
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in
Table 2
and
as illustrated in
Figure 2
. In
Table 3
through
Table 13
, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage
1
1.
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
PIN
True
Asserted
V
IL
/V
OL
PIN
False
Deasserted
V
IH
/V
OH
PIN
True
Asserted
V
IH
/V
OH
PIN
False
Deasserted
V
IL
/V
OL
Functional Group
Number of
Pins
Detailed
Description
Power (V
DD
or V
DDA
)
5
Table 3
Ground (V
SS
or V
SSA
)
6
Table 4
Supply Capacitors
2
Table 5
PLL and Clock
2
Table 6
Interrupt and Program Control
2
Table 7
Pulse Width Modulator (PWM) Port
7
Table 8
Serial Peripheral Interface (SPI) Port
1
1.
Alternately, GPIO pins
4
Table 9
Serial Communications Interface (SCI) Port
1
2
Table 10
Analog-to-Digital Converter (ADC) Port
9
Table 11
Quad Timer Module Port
3
Table 12
JTAG/On-Chip Emulation (OnCE)
6
Table 13
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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