參數(shù)資料
型號(hào): DSPB56366AG120
廠商: Freescale Semiconductor
文件頁數(shù): 15/110頁
文件大?。?/td> 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
產(chǎn)品變化通告: Product Discontinuation 24/Feb/2012
標(biāo)準(zhǔn)包裝: 60
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 120MHz
非易失內(nèi)存: ROM(240 kB)
芯片上RAM: 69kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 110°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
DSP56366 Technical Data, Rev. 3.1
2-8
Freescale Semiconductor
2.6
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 2-8 Interrupt and Mode Control
Signal Name
Type
State
during
Reset
Signal Description
MODA/IRQA
Input
Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into the OMR when the RESET signal is deasserted. If the processor is
in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will
exit the stop state.
This input is 5 V tolerant.
MODB/IRQB
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 5 V tolerant.
MODC/IRQC
Input
Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 5 V tolerant.
MODD/IRQD
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 5 V tolerant.
RESET
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed
in the Reset state and the internal phase generator is reset. The Schmitt-trigger input
allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When
the RESET signal is deasserted, the initial chip operating mode is latched from the
MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during
power up. A stable EXTAL signal must be supplied while RESET is being asserted.
This input is 5 V tolerant.
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