The SHI has five I/O signals that can be con" />
參數(shù)資料
型號(hào)： DSPB56366AG120
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 19/110頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
產(chǎn)品變化通告： Product Discontinuation 24/Feb/2012
標(biāo)準(zhǔn)包裝： 60
系列： DSP56K/Symphony
類(lèi)型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 120MHz
非易失內(nèi)存： ROM（240 kB）
芯片上RAM： 69kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 110°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
DSP56366 Technical Data, Rev. 3.1
2-12
Freescale Semiconductor
2.8
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 2-10 Serial Host Interface Signals
Signal
Name
Signal Type
State during
Reset
Signal Description
SCK
Input or
output
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a
master and a Schmitt-trigger input when the SPI is configured as a slave. When the
SPI is configured as a master, the SCK signal is derived from the internal SHI clock
generator. When the SPI is configured as a slave, the SCK signal is an input, and
the clock signal from the external master synchronizes the data transfer. The SCK
signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal
is not asserted. In both the master and slave SPI devices, data is shifted on one
edge of the SCK signal and is sampled on the opposite edge where data is stable.
Edge polarity is determined by the SPI transfer protocol.
SCL
Input or
output
Tri-stated
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode.
SCL is a Schmitt-trigger input when configured as a slave and an open-drain output
when configured as a master. SCL should be connected to VCC through a pull-up
resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
Input or
output
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the
master data input line. The MISO signal is used in conjunction with the MOSI signal
for transmitting and receiving serial data. This signal is a Schmitt-trigger input when
configured for the SPI Master mode, an output when configured for the SPI Slave
mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted.
An external pull-up resistor is not required for SPI operation.
SDA
Input or
open-drain
output
Tri-stated
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when
receiving and an open-drain output when transmitting. SDA should be connected to
VCC through a pull-up resistor. SDA carries the data for I
2C transactions. The data
in SDA must be stable during the high period of SCL. The data in SDA is only
allowed to change when SCL is low. When the bus is free, SDA is high. The SDA
line is only allowed to change during the time SCL is high in the case of start and
stop events. A high-to-low transition of the SDA line while SCL is high is a unique
situation, and is defined as the start event. A low-to-high transition of SDA while
SCL is high is a unique situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
MOSI
Input or
output
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the
master data output line. The MOSI signal is used in conjunction with the MISO
signal for transmitting and receiving serial data. MOSI is the slave data input line
when the SPI is configured as a slave. This signal is a Schmitt-trigger input when
configured for the SPI Slave mode.
相關(guān)PDF資料
PDF描述
DSPB56367AG150 IC DSP 24BIT 150MHZ 144-LQFP
DSPB56371AF180 IC DSP 24BIT 180MHZ 80-LQFP
DSPB56374AEC IC DSP 24BIT 150MHZ 52-LQFP
DSPB56720CAG DSP 24BIT AUD 200MHZ 144-LQFP
DSPB56724AG DSP 24BIT AUD 250MHZ 144-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56366PV120 制造商:Motorola Inc 功能描述: 制造商:Freescale Semiconductor 功能描述:IC 制造商:MOTOROLA 功能描述:
DSPB56367AG150 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 150Mhz/150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB56367PV150 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 150Mhz/ 150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB5636AG120 制造商:Freescale Semiconductor 功能描述:
DSPB56371AF150 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 150 MHZ VERSION DSPB371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*