參數(shù)資料
型號: DSPB56371AF150
廠商: Freescale Semiconductor
文件頁數(shù): 66/68頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 150MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時鐘速率: 150MHz
非易失內(nèi)存: ROM(384 kB)
芯片上RAM: 264kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 115°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
DSP56371 Overview
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
7
The PCU implements its functions using the following registers:
PC—program counter register
SR—Status register
LA—loop address register
LC—loop counter register
VBA—vector base address register
SZ—stack size register
SP—stack pointer
OMR—operating mode register
SC—stack counter register
The PCU also includes a hardware system stack (SS).
2.4.4
Internal Buses
To provide data exchange between blocks, the following buses are implemented:
Peripheral input/output expansion bus (PIO_EB) to peripherals
Program memory expansion bus (PM_EB) to program memory
X memory expansion bus (XM_EB) to X memory
Y memory expansion bus (YM_EB) to Y memory
Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well
as the memory-mapped registers in the peripherals
DMA data bus (DDB) for carrying DMA data between memories and/or peripherals
DMA address bus (DAB) for carrying DMA addresses to memories and peripherals
Program Data Bus (PDB) for carrying program data throughout the core
X memory Data Bus (XDB) for carrying X data throughout the core
Y memory Data Bus (YDB) for carrying Y data throughout the core
Program address bus (PAB) for carrying program memory addresses throughout the core
X memory address bus (XAB) for carrying X memory addresses throughout the core
Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1.
2.4.5
Direct Memory Access (DMA)
The DMA block has the following features:
Six DMA channels supporting internal and external accesses
One-, two- and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
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