參數(shù)資料
型號(hào): DSPIC30F3013-30I/SP
廠商: Microchip Technology
文件頁(yè)數(shù): 117/161頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 24KB(8K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 651 (CN2011-ZH PDF)
配用: DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F301330ISP
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dsPIC30F2011/2012/3012/3013
DS70139G-page 44
2010 Microchip Technology Inc.
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing
modes
supported
by
most
MCU
instructions, move and accumulator instructions also
support
Register
Indirect
with
Register
Offset
Addressing mode, also referred to as Register Indexed
mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
4.1.4
MAC
INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC
and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand prefetch registers must belong
to the set {W8, W9, W10, W11}. For data reads, W8
and W9 are always directed to the X RAGU. W10 and
W11 are always directed to the Y AGU. The effective
addresses generated (before and after modification)
must, therefore, be valid addresses within X data space
for W8 and W9 and Y data space for W10 and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo Addressing is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces.
Modulo Addressing can operate on any W register
pointer. However, it is not advisable to use W14 or W15
for Modulo Addressing since these two registers are
used as the Stack Frame Pointer and Stack Pointer,
respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain
restrictions on the
buffer
Start
address
(for incrementing
buffers),
or
end
address
(for decrementing buffers) based upon the direction of
the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-2 length. As these buffers
satisfy the Start and the end address criteria, they can
operate in a Bidirectional mode (i.e., address boundary
checks are performed on both the lower and upper
address boundaries).
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for
the
source
and
destination
EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
Note:
Not
all
instructions
support
all
the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Note:
Register Indirect with Register Offset
addressing is only available for W9 (in X
space) and W11 (in Y space).
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