參數(shù)資料
型號: DSPIC30F3013-30I/SP
廠商: Microchip Technology
文件頁數(shù): 83/161頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 24KB(8K x 24)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F301330ISP
PIC18F46J11 FAMILY
DS39932D-page 202
2011 Microchip Technology Inc.
13.1
Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON),
displayed in Register 13-2, is used to control the
Timer1 gate.
REGISTER 13-2:
T1GCON: TIMER1 GATE CONTROL REGISTER (F9Ah)(1)
R/W-0
R-x
R/W-0
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/T1DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GE:
Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1
= Timer1 counting is controlled by the Timer1 gate function
0
= Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL:
Timer1 Gate Polarity bit
1
= Timer1 gate is active-high (Timer1 counts when gate is high)
0
= Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM:
Timer1 Gate Toggle Mode bit
1
= Timer1 Gate Toggle mode is enabled
0
= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM:
Timer1 Gate Single Pulse Mode bit
1
= Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate
0
= Timer1 Gate Single Pulse mode is disabled
bit 3
T1GGO/T1DONE:
Timer1 Gate Single Pulse Acquisition Status bit
1
= Timer1 gate single pulse acquisition is ready, waiting for an edge
0
= Timer1 gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL:
Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by
Timer1 Gate Enable (TMR1GE) bit.
bit 1-0
T1GSS<1:0>:
Timer1 Gate Source Select bits
00
= Timer1 gate pin
01
= Timer0 overflow output
10
= TMR2 to match PR2 output
Note 1:
Programming the T1GCON prior to T1CON is recommended.
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