參數(shù)資料
型號： DSPIC30F3013-30I/SP
廠商： Microchip Technology
文件頁數(shù)： 131/161頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 15
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 24KB（8K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F301330ISP
2010 Microchip Technology Inc.
DS70139G-page 57
dsPIC30F2011/2012/3012/3013
6.3
Writing to the Data EEPROM
To write an EEPROM data location, the following
sequence must be followed:
1.
Erase data EEPROM word.
a)
Select word, data EEPROM erase, and set
WREN bit in NVMCON register.
b)
Write address of word to be erased into
NVMADR.
c)
Enable NVM interrupt (optional).
d)
Write 0x55 to NVMKEY.
e)
Write 0xAA to NVMKEY.
f)
Set the WR bit. This begins erase cycle.
g)
Either poll NVMIF bit or wait for NVMIF
interrupt.
h)
The WR bit is cleared when the erase cycle
ends.
2.
Write data word into data EEPROM write
latches.
3.
Program 1 data word into data EEPROM.
a)
Select word, data EEPROM program, and
set WREN bit in NVMCON register.
b)
Enable NVM write done interrupt (optional).
c)
Write 0x55 to NVMKEY.
d)
Write 0xAA to NVMKEY.
e)
Set the WR bit. This begins program cycle.
f)
Either poll NVMIF bit or wait for NVM
interrupt.
g)
The WR bit is cleared when the write cycle
ends.
The write does not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution. The WREN bit should be kept clear at all
times except when updating the EEPROM. The WREN
bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit does not affect the current write cycle. The
WR bit is inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous
instruction. Both WR and WREN cannot be set with the
same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt or poll this bit. NVMIF
must be cleared by software.
6.3.1
WRITING A WORD OF DATA
EEPROM
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 6-4.
6.3.2
WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 6-4:
DATA EEPROM WORD WRITE
; Point to data memory
MOV
#LOW_ADDR_WORD,W0
; Init pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
MOV
#LOW(WORD),W2
; Get data
TBLWTL
W2,[ W0]
; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
#0x4004,W0
MOV
W0,NVMCON
; Operate key to allow write operation
DISI
#5
; Block all interrupts with priority <7 for
; next 5 instructions
MOV
#0x55,W0
MOV
W0,NVMKEY
; Write the 0x55 key
MOV
#0xAA,W1
MOV
W1,NVMKEY
; Write the 0xAA key
BSET
NVMCON,#WR
; Initiate program sequence
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
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