參數(shù)資料
型號： DSPIC30F3013-30I/SP
廠商： Microchip Technology
文件頁數(shù)： 96/161頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 15
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 24KB（8K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F301330ISP
2010 Microchip Technology Inc.
DS70139G-page 25
dsPIC30F2011/2012/3012/3013
2.4.1
MULTIPLIER
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17 x 17-bit
multiplier/scaler
is
a
33-bit
value
which
is
sign-extended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaking, the range of an N-bit two’s complement
integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
range is -32768 (0x8000) to 32767 (0x7FFF) including
‘0’.
For
a
32-bit
integer,
the
data
range
is
-2,147,483,648
(0x8000 0000)
to
2,147,483,645
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSB is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’
and has a precision of 3.01518x10-5. In Fractional
mode, the 16x16 multiply operation generates a 1.31
product, which has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiplies.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result. Word operands direct a 32-bit result to the
specified register(s) in the W array.
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The
data
accumulator
consists
of
a
40-bit
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
through the barrel shifter prior to accumulation.
2.4.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
Overflow from bit 39: This is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: This is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation if selected. It uses
the result of the adder, the overflow Status bits
described above, and the mode control bits SATA/B
(CORCON<7:6>) and ACCSAT (CORCON<4>)
to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
OA: ACCA overflowed into guard bits
OB: ACCB overflowed into guard bits
SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB: Logical OR of OA and OB
SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic
warning
trap
when
set
and
the
corresponding overflow trap flag enable bit (OVATE,
OVBTE) in the INTCON1 register (refer to Section 8.0
“Interrupts”) is set. This allows the user to take
immediate action, for example, to correct system gain.
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