參數(shù)資料
型號: DSPIC30F3013-30I/SP
廠商: Microchip Technology
文件頁數(shù): 160/161頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 24KB(8K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F301330ISP
2010 Microchip Technology Inc.
DS70139G-page 83
dsPIC30F2011/2012/3012/3013
11.0
INPUT CAPTURE MODULE
This section describes the input capture module and
associated operational modes. The features provided
by this module are useful in applications requiring
frequency (period) and pulse measurement.
Figure 11-1 depicts a block diagram of the input
capture module. Input capture is useful for such modes
as:
Frequency/Period/Pulse Measurements
Additional Sources of External Interrupts
Important operational features of the input capture
module are:
Simple Capture Event mode
Timer2 and Timer3 mode selection
Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the IC1CON and IC2CON registers.
The dsPIC30F2011/2012/3012/3013 devices have two
capture channels.
11.1
Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
Capture every falling edge
Capture every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
Capture every rising and falling edge
These simple Input Capture modes are configured by
setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).
11.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings
specified by bits ICM<2:0> (ICxCON<2:0>). Whenever
the capture channel is turned off, the prescaler counter
is cleared. In addition, any Reset clears the prescaler
counter.
FIGURE 11-1:
INPUT CAPTURE MODE BLOCK DIAGRAM(1)
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
ICxBUF
Prescaler
ICx pin
ICM<2:0>
Mode Select
3
Note 1:
Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture
channel (1 or 2).
10
Set Flag
ICxIF
ICTMR
T2_CNT
T3_CNT
Edge
Detection
Logic
Clock
Synchronizer
1, 4, 16
From GP Timer Module
16
FIFO
R/W
Logic
ICI<1:0>
ICBNE, ICOV
ICxCON
Interrupt
Logic
Set Flag
ICxIF
Data Bus
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