181
SAM4CP [DATASHEET]
43051E–ATPL–08/14
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt
signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change.
Otherwise, the state of the interrupt changes to inactive.
12.8.2 NVIC Design Hints and Tips
Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned accesses
to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking
that interrupt.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table
are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the
“Vector Table
Offset Register”
.
12.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the
following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
The array ISER[0] to ISER[1] corresponds to the registers ISER0 - ISER1.
The array ICER[0] to ICER[1] corresponds to the registers ICER0 - ICER1.
The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0 - ISPR1.
The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0 - ICPR1.
The array IABR[0] to IABR[1] corresponds to the registers IABR0 - IABR1.
Table 12-30. CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function
Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn)
Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn)
Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn)
Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn)
Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn)
Read priority of IRQn
void NVIC_SystemReset (void)
Reset the system