SAM4CP [DATASHEET]
43051E–ATPL–08/14
22
After this step, the Core voltage regulator is shut down and the SHDN pin goes low. All the digital internal logic (cores,
peripherals and memories) is not powered. The LCD controller can be enabled if needed before entering backup mode.
Whether the VROFF bit or the WFE instruction was used to enter backup mode, the system exits backup mode if one of
the following enabled wake-up events occurs:
WKUP[0-15] pins
Force Wake-up pin
VDDIO Supply Monitor (if VDDIO is present, and VDDIO Supply falling)
Anti-tamper event detection
RTC alarm
RTT alarm
After exiting backup mode, the device is in the reset state. Only the configuration of the backup area peripherals remains
unchanged.
Note that the device does not automatically enter backup mode if VDDIN is disconnected, or if it falls below minimum
voltage. The Shutdown pin (SHDN) remains high in this case.
For current consumption in backup mode, refer to the section “Electrical Characteristics”.
5.5.2
Wait Mode
The purpose of wait mode is to achieve very low power consumption while maintaining the whole device in a powered
state for a start-up time of less than 10
μ
s. For current consumption in wait mode, refer to the electrical characteristics of
this datasheet.
In this mode, the bus and peripheral clocks of Sub-system 0 and Sub-system 1 (MCK/CPBMCK), the clocks of Core 0
and Core 1 (HCLK/CPHCLK) are stopped when the Entering Wait Mode sequence is performed (see
Section 5.5.2.1
).
However, the power supply of core, peripherals and memories is maintained using the standby mode of the core voltage
regulator.
The SAM4CP is able to handle external and internal events in order to perform a wake-up. This is done by configuring
the external WKUPx lines as fast startup wake-up pins (refer to
Section 5.7 “Fast Start-up”
). RTC alarm, RTT alarm and
anti-tamper events can wake the device up as well.
The Wait mode can be used together with the Flash in Read-Idle mode, Standby mode or Deep Power mode to further
reduce the current consumption. Flash in Read-Idle mode provides a faster start-up and the Standby mode offers a lower
power consumption. For further details, see the “Low-power Wake-up Time” section of the product electrical
characteristics.
5.5.2.1 Entering and Exiting Wait Mode
1.
Stop Sub-system 1.
2.
Select the 4/8/12 MHz fast RC Oscillator as Main Clock
(1)
.
3.
Depending on the application, set the PIO lines in the correct mode and configuration (input pull-up or pull-down,
output low or high level).
4.
Disable the Main Crystal Oscillator (enabled by SAM-BA boot if device is booting from ROM).
5.
Configure PA30/PA31 (XIN/XOUT) into PIO mode according to their use.
6.
Disable JTAG lines via SFR1 register in Matrix 0 (by default, internal pull-up or pull-down is disabled on JTAG
lines).
7.
Set the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)
(2)
.
8.
Set the Flash Wait State (FWS) bit in the EEFC Flash Mode Register to 0.
9.
Select one of the following methods to complete the sequence:
a.
To enter wait mode using the WAITMODE bit:
Set the WAITMODE bit to 1 in the PMC Main Oscillator Register (CKGR_MOR).
Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR).