976
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Each Region descriptor supports gathering of data through the use of the Secondary List. Unlike the Main List, the
Secondary List cannot modify the configuration attributes of the Region. When the end of the Secondary List has been
encountered, the ICM returns to the Main List. Memory integrity Monitoring can be considered as a background service
and the mandatory bandwidth shall be very limited. In order to limit the ICM memory bandwidth, use the BBC field of the
ICM_CFG register to control ICM memory load.
Figure 42-4.
Region Descriptor
The ICM integrates a Secure Hash Algorithm Engine (SHA). This module requires a message padded according to
FIPS180-2 specification. The SHA module produces an N-bit message digest each time a block is read and a processing
period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256.
42.5.1 ICM Region Descriptor Structure
The ICM Region Descriptor Area is a contiguous Area of system memory that the controller and the processor can
access. When the ICM controller is activated, the controller performs a descriptor fetch operation at *(ICM_DSCR)
address. If the Main List contains more than one descriptor (i.e. more than one region is to be monitored), the fetch
address is *(ICM_DSCR) + (RID<<4) where RID is the region identifier.
End of Region 0
ICMDSCR
Region 0 Descriptor
Region 1 Descriptor
Region ADDR
Region CFG
Region CTRL
Region NEXT
0x000
0x004
0x008
0x00C
Optional Region 0 Secondary List
Region ADDR
Unused
Region CTRL
Region NEXT
0x000
0x004
0x008
0x00C
Region 2 Descriptor
Region 3 Descriptor
Main List
Table 42-2.
Region Descriptor Structure (Main List)
Address
Structure Member
Name
ICM_DSCR+0x000+RID*(0x10)
ICM Region Start Address
ICM_RADDR
ICM_DSCR+0x004+RID*(0x10)
ICM Region Configuration
ICM_RCFG
ICM_DSCR+0x008+RID*(0x10)
ICM Region Control
ICM_RCTRL
ICM_DSCR+0x00C+RID*(0x10)
ICM Region Next Address
ICM_RNEXT