參數(shù)資料
型號(hào)： EM78P568
廠商： ELAN Microelctronics Corp .
英文描述： 8-BIT OTP MICRO-CONTROLLER
中文描述： 8位檢察官微控制器
文件頁數(shù)： 19/61頁
文件大?。?/td> 568K
代理商： EM78P568
EM78P568
8-bit OTP Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
01/31/2004 V4.7
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Data RAM data register)
7
6
5
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit
0 ~ Bit 1 (RAM_B0 ~ RAM_B1).
RA (PLL, Main clock selection, Comparator flag, Watchdog timer, DAC input data buffer,
LCD option)
PAGE0 (PLL enable bit, Main clock selection bits, Comparator control bits, Watchdog timer enable bit)
7
6
5
4
3
IDLE
PLLEN
CLK2
CLK1
CLK0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
Bit 0(WDTEN) : Watch dog control bit
0/1
disable/enable
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
Bit 1(CMPREF) : Comparator’s reference voltage source selection bit
0
Comparator’s reference voltage is driven from internal bias resistor string. This reference voltage level
can be set by RD PAGE0 bit 0 ~ bit 5 (CMP_B0 ~ CMP_B5).
1
Comparator’s reference voltage is driven from external bias. This reference voltage input is CMP3/P65
pin. Also IOC6 PAGE1 bit 2(CMP63/P63) should be set to “1”.
Bit 2(CMPFLAG) : Output of the comparator
0
Input voltage < reference voltage
1
input voltage > reference voltage
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
1
0
0
0
32.768kHz
1
0
0
1
32.768kHz
1
0
1
0
32.768kHz
1
0
1
1
32.768kHz
1
1
0
0
32.768kHz
1
1
0
1
32.768kHz
1
1
1
0
32.768kHz
1
1
1
1
32.768kHz
0
don’t care
don’t care
32.768kHz
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1
disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
4
3
2
1
0
R/W
R/W
R/W
R/W
2
1
0
CMPFLAG CMPREF WDTEN
R
R/W-0
R/W-0
MAIN clock
447.829kHz
895.658kHz
1.791MHz
3.582MHz
7.165MHz
10.747MHz
14.331MHz
17.913MHz
don’t care
CPU clock
447.829kHz (Normal mode)
895.658kHz (Normal mode)
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
10.747MHz (Normal mode)
14.331MHz (Normal mode)
17.913MHz (Normal mode)
32.768kHz (Green mode)
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